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When mass erase is disabled, mass erase via the debugger is blocked.
Chapter 8 Security
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors
197
196
198
Table of Contents
Default Chapter
3
Table of Contents
3
Chapter 1 About this Document
47
Overview
47
Purpose
47
Audience
47
Conventions
47
Numbering Systems
47
Typographic Notation
48
Special Terms
48
Chapter 2 Introduction
49
Overview
49
Module Functional Categories
49
ARM® Cortex®-M4 Core Modules
50
System Modules
51
Memories and Memory Interfaces
52
Clocks
52
Security and Integrity Modules
53
Analog Modules
53
Timer Modules
53
Communication Interfaces
54
Human-Machine Interfaces
55
Orderable Part Numbers
55
Chapter 3 Chip Configuration
57
Introduction
57
Core Modules
57
ARM Cortex-M4 Core Configuration
57
Nested Vectored Interrupt Controller (NVIC) Configuration
59
Asynchronous Wake-Up Interrupt Controller (AWIC) Configuration
65
FPU Configuration
66
JTAG Controller Configuration
66
System Modules
67
SIM Configuration
67
System Mode Controller (SMC) Configuration
68
PMC Configuration
69
Low-Leakage Wake-Up Unit (LLWU) Configuration
69
MCM Configuration
71
Crossbar-Light Switch Configuration
71
Peripheral Bridge Configuration
73
DMA Request Multiplexer Configuration
74
DMA Controller Configuration
77
External Watchdog Monitor (EWM) Configuration
78
Watchdog Configuration
80
Clock Modules
81
MCG Configuration
81
OSC Configuration
83
RTC OSC Configuration
83
Memories and Memory Interfaces
84
Flash Memory Configuration
84
Flash Memory Controller Configuration
87
SRAM Configuration
87
System Register File Configuration
89
VBAT Register File Configuration
90
Ezport Configuration
91
Flexbus Configuration
92
Security
95
CRC Configuration
95
RNG Configuration
96
Analog
97
16-Bit SAR ADC Configuration
97
CMP Configuration
104
12-Bit DAC Configuration
106
VREF Configuration
107
Timers
108
PDB Configuration
108
Flextimer Configuration
111
PIT Configuration
117
Low-Power Timer Configuration
118
RTC Configuration
120
Communication Interfaces
121
Universal Serial Bus (USB) FS Subsystem
121
SPI Configuration
126
I2C Configuration
130
UART Configuration
131
LPUART Configuration
133
I2S Configuration
134
Human-Machine Interfaces
137
GPIO Configuration
137
Chapter 4 Memory Map
139
Introduction
139
System Memory Map
139
Aliased Bit-Band Regions
141
Flash Access Control Introduction
142
Flash Memory Map
142
Alternate Non-Volatile IRC User Trim Description
143
SRAM Memory Map
143
Peripheral Bridge (AIPS-Lite) Memory Map
144
Read-After-Write Sequence and Required Serialization of Memory Operations
144
Peripheral Bridge 0 (AIPS-Lite 0) Memory Map
144
Private Peripheral Bus (PPB) Memory Map
148
Chapter 5 Clock Distribution
151
Introduction
151
Programming Model
151
High-Level Device Clocking Diagram
151
Clock Definitions
152
Device Clock Summary
153
Internal Clocking Requirements
156
Clock Divider Values after Reset
157
VLPR Mode Clocking
157
Clock Gating
158
Module Clocks
158
PMC 1-Khz LPO Clock
160
IRC 48Mhz Clock
160
WDOG Clocking
161
Debug Trace Clock
161
PORT Digital Filter Clocking
162
LPTMR Clocking
162
RTC_CLKOUT and CLKOUT32K Clocking
163
USB FS OTG Controller Clocking
164
UART Clocking
165
LPUART0 Clocking
165
I2S/SAI Clocking
166
Chapter 6 Reset and Boot
169
Introduction
169
Reset
170
Power-On Reset (POR)
170
System Reset Sources
170
MCU Resets
174
Reset Pin
175
Debug Resets
176
Boot
177
Boot Sources
177
Boot Options
177
FOPT Boot Options
178
Boot Sequence
179
Chapter 7 Power Management
181
Introduction
181
Clocking Modes
181
Partial Stop
181
DMA Wakeup
182
Compute Operation
183
Peripheral Doze
184
Clock Gating
185
Power Modes Description
185
Entering and Exiting Power Modes
187
Power Mode Transitions
188
Power Modes Shutdown Sequencing
189
Flash Program Restrictions
190
Module Operation in Low Power Modes
190
Chapter 8 Security
195
Introduction
195
Flash Security
195
Security Interactions with Other Modules
196
Security Interactions with Flexbus
196
Security Interactions with Ezport
196
Security Interactions with Debug
196
Chapter 9 Debug
199
Introduction
199
References
201
The Debug Port
201
JTAG-To-SWD Change Sequence
202
JTAG-To-Cjtag Change Sequence
202
Debug Port Pin Descriptions
203
System TAP Connection
203
IR Codes
204
JTAG Status and Control Registers
204
MDM-AP Control Register
205
MDM-AP Status Register
207
Debug Resets
208
Ahb-Ap
209
Itm
209
Core Trace Connectivity
210
Tpiu
210
Dwt
210
Debug in Low Power Modes
211
Debug Module State in Low Power Modes
211
Debug & Security
212
Chapter 10 Signal Multiplexing and Signal Descriptions
213
Introduction
213
Signal Multiplexing Integration
213
Port Control and Interrupt Module Features
214
Clock Gating
215
Signal Multiplexing Constraints
215
Pinout
215
K22F Signal Multiplexing and Pin Assignments
215
K22 Pinouts
222
Module Signal Description Tables
228
Core Modules
229
System Modules
229
Clock Modules
230
Memories and Memory Interfaces
230
Analog
233
Timer Modules
234
Communication Interfaces
236
Human-Machine Interfaces (HMI)
238
Chapter 11 Port Control and Interrupts (PORT)
239
Introduction
239
Overview
239
Features
239
Modes of Operation
240
External Signal Description
241
Detailed Signal Description
241
Memory Map and Register Definition
241
Pin Control Register N (Portx_Pcrn)
248
Global Pin Control Low Register (Portx_Gpclr)
251
Global Pin Control High Register (Portx_Gpchr)
251
Interrupt Status Flag Register (Portx_Isfr)
252
Digital Filter Enable Register (Portx_Dfer)
252
Digital Filter Clock Register (Portx_Dfcr)
253
Digital Filter Width Register (Portx_Dfwr)
253
Functional Description
254
Pin Control
254
Global Pin Control
255
External Interrupts
255
Digital Filter
256
Chapter 12 System Integration Module (SIM)
259
Introduction
259
Features
259
Memory Map and Register Definition
260
System Options Register 1 (SIM_SOPT1)
261
SOPT1 Configuration Register (SIM_SOPT1CFG)
263
System Options Register 2 (SIM_SOPT2)
264
System Options Register 4 (SIM_SOPT4)
266
System Options Register 5 (SIM_SOPT5)
269
System Options Register 7 (SIM_SOPT7)
271
System Options Register 8 (SIM_SOPT8)
273
System Device Identification Register (SIM_SDID)
275
System Clock Gating Control Register 4 (SIM_SCGC4)
277
System Clock Gating Control Register 5 (SIM_SCGC5)
279
System Clock Gating Control Register 6 (SIM_SCGC6)
281
System Clock Gating Control Register 7 (SIM_SCGC7)
284
System Clock Divider Register 1 (SIM_CLKDIV1)
285
System Clock Divider Register 2 (SIM_CLKDIV2)
287
Flash Configuration Register 1 (SIM_FCFG1)
288
Flash Configuration Register 2 (SIM_FCFG2)
289
Unique Identification Register High (SIM_UIDH)
290
Unique Identification Register MID-High (SIM_UIDMH)
290
Unique Identification Register MID Low (SIM_UIDML)
291
Unique Identification Register Low (SIM_UIDL)
291
Functional Description
291
Chapter 13 Kinetis Flashloader
293
Chip-Specific Information
293
Introduction
293
Functional Description
295
Memory Maps
295
Start-Up Process
295
Clock Configuration
296
Flashloader Protocol
297
Flashloader Packet Types
301
Flashloader Command API
308
Peripherals Supported
327
I2C Peripheral
328
SPI Peripheral
329
UART Peripheral
331
USB Peripheral
334
Get/Setproperty Command Properties
336
Property Definitions
338
Kinetis Flashloader Status Error Codes
339
Reset Control Module (RCM)
341
Introduction
341
Reset Memory Map and Register Descriptions
341
Reset Memory Map/Register Descriptions
341
System Reset Status Register 0 (RCM_SRS0)
342
System Reset Status Register 1 (RCM_SRS1)
343
Reset Pin Filter Control Register (RCM_RPFC)
345
Reset Pin Filter Width Register (RCM_RPFW)
346
Mode Register (RCM_MR)
347
Sticky System Reset Status Register 0 (RCM_SSRS0)
348
Sticky System Reset Status Register 1 (RCM_SSRS1)
349
Chapter 15 System Mode Controller (SMC)
351
Introduction
351
Modes of Operation
351
Memory Map and Register Descriptions
353
Power Mode Protection Register (SMC_PMPROT)
354
Power Mode Control Register (SMC_PMCTRL)
355
Stop Control Register (SMC_STOPCTRL)
357
Power Mode Status Register (SMC_PMSTAT)
358
Functional Description
359
Power Mode Transitions
359
Power Mode Entry/Exit Sequencing
362
Run Modes
364
Wait Modes
366
Stop Modes
366
Debug in Low Power Modes
370
Chapter 16 Power Management Controller (PMC)
371
Introduction
371
Features
371
Low-Voltage Detect (LVD) System
371
LVD Reset Operation
372
LVD Interrupt Operation
372
Low-Voltage Warning (LVW) Interrupt Operation
372
I/O Retention
373
Memory Map and Register Descriptions
373
Low Voltage Detect Status and Control 1 Register (PMC_LVDSC1)
374
Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2)
375
Regulator Status and Control Register (PMC_REGSC)
376
Chapter 17 Low-Leakage Wakeup Unit (LLWU)
379
Introduction
379
Features
379
Modes of Operation
380
Block Diagram
381
LLWU Signal Descriptions
382
Memory Map/Register Definition
382
LLWU Pin Enable 1 Register (LLWU_PE1)
383
LLWU Pin Enable 2 Register (LLWU_PE2)
384
LLWU Pin Enable 3 Register (LLWU_PE3)
385
LLWU Pin Enable 4 Register (LLWU_PE4)
386
LLWU Module Enable Register (LLWU_ME)
387
LLWU Flag 1 Register (LLWU_F1)
389
LLWU Flag 2 Register (LLWU_F2)
391
LLWU Flag 3 Register (LLWU_F3)
392
LLWU Pin Filter 1 Register (LLWU_FILT1)
394
LLWU Pin Filter 2 Register (LLWU_FILT2)
395
Functional Description
396
LLS Mode
397
VLLS Modes
397
Initialization
397
Chapter 18 Miscellaneous Control Module (MCM)
399
Introduction
399
Features
399
Memory Map/Register Descriptions
399
Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
400
Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)
400
Crossbar Switch (AXBS) Control Register (MCM_PLACR)
401
Interrupt Status and Control Register (MCM_ISCR)
401
Compute Operation Control Register (MCM_CPO)
404
Functional Description
405
Interrupts
405
Chapter 19 Crossbar Switch Lite (AXBS-Lite)
407
Introduction
407
Features
407
Memory Map / Register Definition
408
Functional Description
408
General Operation
408
Arbitration
409
Initialization/Application Information
410
Chapter 20 Peripheral Bridge (AIPS-Lite)
411
Introduction
411
Features
411
General Operation
411
Memory Map/Register Definition
412
Functional Description
412
Access Support
412
Chapter 21 Direct Memory Access Multiplexer (DMAMUX)
413
Introduction
413
Overview
413
Features
414
Modes of Operation
414
External Signal Description
415
Memory Map/Register Definition
415
Channel Configuration Register (Dmamux_Chcfgn)
416
Functional Description
417
DMA Channels with Periodic Triggering Capability
417
DMA Channels with no Triggering Capability
419
Always-Enabled DMA Sources
420
Initialization/Application Information
421
Reset
421
Enabling and Configuring Sources
421
Chapter 22 Enhanced Direct Memory Access (Edma)
425
Introduction
425
Edma System Block Diagram
425
Block Parts
426
Features
427
Modes of Operation
428
Memory Map/Register Definition
429
TCD Memory
429
TCD Initialization
429
TCD Structure
430
Reserved Memory and Bit Fields
430
Control Register (DMA_CR)
441
Error Status Register (DMA_ES)
444
Enable Request Register (DMA_ERQ)
446
Enable Error Interrupt Register (DMA_EEI)
448
Clear Enable Error Interrupt Register (DMA_CEEI)
450
Set Enable Error Interrupt Register (DMA_SEEI)
451
Clear Enable Request Register (DMA_CERQ)
452
Set Enable Request Register (DMA_SERQ)
453
Clear DONE Status Bit Register (DMA_CDNE)
454
Set START Bit Register (DMA_SSRT)
455
Clear Error Register (DMA_CERR)
456
Clear Interrupt Request Register (DMA_CINT)
457
Interrupt Request Register (DMA_INT)
458
Error Register (DMA_ERR)
460
Hardware Request Status Register (DMA_HRS)
463
Enable Asynchronous Request in Stop Register (DMA_EARS)
466
Channel N Priority Register (Dma_Dchprin)
468
TCD Source Address (Dma_Tcdn_Saddr)
469
TCD Signed Source Address Offset (Dma_Tcdn_Soff)
469
TCD Transfer Attributes (Dma_Tcdn_Attr)
470
TCD Minor Byte Count (Minor Loop Mapping Disabled) (Dma_Tcdn_Nbytes_Mlno)
471
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
472
(Dma_Tcdn_Nbytes_Mloffno)
472
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
473
(Dma_Tcdn_Nbytes_Mloffyes)
473
TCD Last Source Address Adjustment (Dma_Tcdn_Slast)
474
TCD Destination Address (Dma_Tcdn_Daddr)
475
TCD Signed Destination Address Offset (Dma_Tcdn_Doff)
475
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (Dma_Tcdn_Citer_Elinkyes)
476
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (Dma_Tcdn_Citer_Elinkno)
477
TCD Last Destination Address Adjustment/Scatter Gather Address (Dma_Tcdn_Dlastsga)
478
TCD Control and Status (Dma_Tcdn_Csr)
479
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (Dma_Tcdn_Biter_Elinkyes)
481
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (Dma_Tcdn_Biter_Elinkno)
482
Functional Description
483
Edma Basic Data Flow
483
Fault Reporting and Handling
486
Channel Preemption
489
Performance
489
Initialization/Application Information
493
Edma Initialization
493
Programming Errors
495
Arbitration Mode Considerations
496
Performing DMA Transfers
496
Monitoring Transfer Descriptor Status
500
Channel Linking
502
Dynamic Programming
503
Lockstep
507
Chapter 23 External Watchdog Monitor (EWM)
509
Introduction
509
Features
509
Modes of Operation
510
Block Diagram
511
EWM Signal Descriptions
512
Memory Map/Register Definition
512
Control Register (EWM_CTRL)
512
Service Register (EWM_SERV)
513
Compare Low Register (EWM_CMPL)
513
Compare High Register (EWM_CMPH)
514
Clock Prescaler Register (EWM_CLKPRESCALER)
515
Functional Description
515
The Ewm_Out Signal
515
The Ewm_In Signal
516
EWM Counter
517
EWM Compare Registers
517
EWM Refresh Mechanism
517
EWM Interrupt
518
Counter Clock Prescaler
518
Chapter 24 Watchdog Timer (WDOG)
519
Introduction
519
Features
519
Functional Overview
520
Unlocking and Updating the Watchdog
522
Watchdog Configuration Time (WCT)
523
Refreshing the Watchdog
524
Windowed Mode of Operation
524
Watchdog Disabled Mode of Operation
524
Debug Modes of Operation
525
Testing the Watchdog
525
Quick Test
526
Byte Test
526
Backup Reset Generator
527
Generated Resets and Interrupts
528
Memory Map and Register Definition
528
Watchdog Status and Control Register High (WDOG_STCTRLH)
529
Watchdog Status and Control Register Low (WDOG_STCTRLL)
531
Watchdog Time-Out Value Register High (WDOG_TOVALH)
531
Watchdog Time-Out Value Register Low (WDOG_TOVALL)
532
Watchdog Window Register High (WDOG_WINH)
532
Watchdog Window Register Low (WDOG_WINL)
533
Watchdog Refresh Register (WDOG_REFRESH)
533
Watchdog Unlock Register (WDOG_UNLOCK)
533
Watchdog Timer Output Register High (WDOG_TMROUTH)
534
Watchdog Timer Output Register Low (WDOG_TMROUTL)
534
Watchdog Reset Count Register (WDOG_RSTCNT)
535
Watchdog Prescaler Register (WDOG_PRESC)
535
Watchdog Operation with 8-Bit Access
535
General Guideline
535
Refresh and Unlock Operations with 8-Bit Access
536
Restrictions on Watchdog Operation
537
Chapter 25 Multipurpose Clock Generator (MCG)
539
Introduction
539
Features
539
Modes of Operation
543
External Signal Description
543
Memory Map/Register Definition
543
MCG Control 1 Register (MCG_C1)
544
MCG Control 2 Register (MCG_C2)
545
MCG Control 3 Register (MCG_C3)
546
MCG Control 4 Register (MCG_C4)
547
MCG Control 5 Register (MCG_C5)
548
MCG Control 6 Register (MCG_C6)
549
MCG Status Register (MCG_S)
551
MCG Status and Control Register (MCG_SC)
552
MCG Auto Trim Compare Value High Register (MCG_ATCVH)
554
MCG Auto Trim Compare Value Low Register (MCG_ATCVL)
554
MCG Control 7 Register (MCG_C7)
554
MCG Control 8 Register (MCG_C8)
555
MCG Control 12 Register (MCG_C12)
556
MCG Status 2 Register (MCG_S2)
556
MCG Test 3 Register (MCG_T3)
557
Functional Description
557
MCG Mode State Diagram
557
Low-Power Bit Usage
561
MCG Internal Reference Clocks
561
External Reference Clock
562
MCG Fixed Frequency Clock
563
MCG PLL Clock
563
MCG Auto TRIM (ATM)
563
Initialization / Application Information
564
MCG Module Initialization Sequence
564
Using a 32.768 Khz Reference
567
MCG Mode Switching
567
Chapter 26 Oscillator (OSC)
577
Introduction
577
Features and Modes
577
Block Diagram
578
OSC Signal Descriptions
578
External Crystal / Resonator Connections
579
External Clock Connections
580
Memory Map/Register Definitions
581
OSC Memory Map/Register Definition
581
Functional Description
583
OSC Module States
583
OSC Module Modes
585
Counter
587
Reference Clock Pin Requirements
587
Reset
587
Low Power Modes Operation
588
Interrupts
588
Chapter 27 RTC Oscillator (OSC32K)
589
Introduction
589
Features and Modes
589
Block Diagram
589
RTC Signal Descriptions
590
EXTAL32 - Oscillator Input
590
XTAL32 - Oscillator Output
590
External Crystal Connections
591
Memory Map/Register Descriptions
591
Functional Description
591
Reset Overview
592
Interrupts
592
Chapter 28 Flash Memory Controller (FMC)
593
Introduction
593
Overview
593
Features
594
Modes of Operation
594
External Signal Description
594
Memory Map and Register Descriptions
594
Flash Access Protection Register (FMC_PFAPR)
600
Flash Bank 0 Control Register (FMC_PFB0CR)
602
Flash Bank 1 Control Register (FMC_PFB1CR)
605
Cache Tag Storage (Fmc_Tagvdw0Sn)
607
Cache Tag Storage (Fmc_Tagvdw1Sn)
608
Cache Tag Storage (Fmc_Tagvdw2Sn)
609
Cache Tag Storage (Fmc_Tagvdw3Sn)
610
Cache Data Storage (Upper Word) (Fmc_Dataw0Snu)
610
Cache Data Storage (Lower Word) (Fmc_Dataw0Snl)
611
Cache Data Storage (Upper Word) (Fmc_Dataw1Snu)
611
Cache Data Storage (Lower Word) (Fmc_Dataw1Snl)
612
Cache Data Storage (Upper Word) (Fmc_Dataw2Snu)
612
Cache Data Storage (Lower Word) (Fmc_Dataw2Snl)
613
Cache Data Storage (Upper Word) (Fmc_Dataw3Snu)
613
Cache Data Storage (Lower Word) (Fmc_Dataw3Snl)
614
Functional Description
614
Default Configuration
614
Configuration Options
615
Speculative Reads
615
Flash Access Control (FAC) Function
616
Initialization and Application Information
627
Chapter 29 Flash Memory Module (FTFA)
629
Introduction
629
Features
630
Block Diagram
630
Glossary
631
External Signal Description
632
Memory Map and Registers
633
Flash Configuration Field Description
633
Program Flash IFR Map
633
Register Descriptions
634
Functional Description
648
Flash Protection
648
Flash Access Protection
648
Interrupts
650
Flash Operation in Low-Power Modes
651
Functional Modes of Operation
651
Flash Reads and Ignored Writes
651
Read While Write (RWW)
652
Flash Program and Erase
652
Flash Command Operations
652
Margin Read Commands
658
Flash Command Description
659
Security
677
Reset Sequence
679
Overview
681
Chapter 30
682
Block Diagram
682
Features
682
Modes of Operation
682
External Signal Descriptions
683
Ezport Clock (EZP_CK)
683
Ezport Chip Select (EZP_CS)
684
Ezport Serial Data in (EZP_D)
684
Ezport Serial Data out (EZP_Q)
684
Command Definition
684
Command Descriptions
685
Flash Memory Map for Ezport Access
692
Chapter 31 External Bus Interface (Flexbus)
693
Introduction
693
Definition
693
Features
694
Signal Descriptions
694
Memory Map/Register Definition
696
Chip Select Address Register (Fb_Csarn)
697
Chip Select Mask Register (Fb_Csmrn)
698
Chip Select Control Register (Fb_Cscrn)
699
Chip Select Port Multiplexing Control Register (FB_CSPMCR)
702
Functional Description
703
Use Cases
703
Address Comparison
704
Address Driven on Address Bus
704
Connecting Address/Data Lines
704
Bit Ordering
705
Data Transfer Signals
705
Signal Transitions
705
Data-Byte Alignment and Physical Connections
705
Address/Data Bus Multiplexing
707
Data Transfer States
708
Flexbus Timing Examples
709
Burst Cycles
728
Extended Transfer Start/Address Latch Enable
737
Bus Errors
738
Initialization/Application Information
739
Initializing a Chip-Select
739
Reconfiguring a Chip-Select
739
Chapter 32 Cyclic Redundancy Check (CRC)
741
Introduction
741
Features
741
Block Diagram
741
Modes of Operation
742
Memory Map and Register Descriptions
742
CRC Data Register (CRC_DATA)
743
CRC Polynomial Register (CRC_GPOLY)
744
CRC Control Register (CRC_CTRL)
744
Functional Description
745
CRC Initialization/Reinitialization
745
CRC Calculations
746
Transpose Feature
747
CRC Result Complement
749
Chapter 33 Random Number Generator Accelerator (RNGA)
751
Introduction
751
Overview
751
Modes of Operation
752
Entering Normal Mode
752
Entering Sleep Mode
752
Memory Map and Register Definition
753
RNGA Control Register (RNG_CR)
753
RNGA Status Register (RNG_SR)
755
RNGA Entropy Register (RNG_ER)
757
RNGA Output Register (RNG_OR)
757
Functional Description
758
Output (OR) Register
758
Core Engine / Control Logic
758
Initialization/Application Information
759
Chapter 34 Analog-To-Digital Converter (ADC)
761
Introduction
761
Features
761
Block Diagram
762
ADC Signal Descriptions
764
Analog Power (VDDA)
765
Analog Ground (VSSA)
765
Voltage Reference Select
765
Analog Channel Inputs (Adx)
766
Differential Analog Channel Inputs (Dadx)
766
Memory Map and Register Definitions
766
ADC Status and Control Registers 1 (Adcx_Sc1N)
768
ADC Configuration Register 1 (Adcx_Cfg1)
772
ADC Configuration Register 2 (Adcx_Cfg2)
773
ADC Data Result Register (Adcx_Rn)
774
Compare Value Registers (Adcx_Cvn)
776
Status and Control Register 2 (Adcx_Sc2)
777
Status and Control Register 3 (Adcx_Sc3)
779
ADC Offset Correction Register (Adcx_Ofs)
780
ADC Plus-Side Gain Register (Adcx_Pg)
781
ADC Minus-Side Gain Register (Adcx_Mg)
781
ADC Plus-Side General Calibration Value Register (Adcx_Clpd)
782
ADC Plus-Side General Calibration Value Register (Adcx_Clps)
783
ADC Plus-Side General Calibration Value Register (Adcx_Clp4)
783
ADC Plus-Side General Calibration Value Register (Adcx_Clp3)
784
ADC Plus-Side General Calibration Value Register (Adcx_Clp2)
784
ADC Plus-Side General Calibration Value Register (Adcx_Clp1)
785
ADC Plus-Side General Calibration Value Register (Adcx_Clp0)
785
ADC Minus-Side General Calibration Value Register (Adcx_Clmd)
786
ADC Minus-Side General Calibration Value Register (Adcx_Clms)
786
ADC Minus-Side General Calibration Value Register (Adcx_Clm4)
787
ADC Minus-Side General Calibration Value Register (Adcx_Clm3)
787
ADC Minus-Side General Calibration Value Register (Adcx_Clm2)
788
ADC Minus-Side General Calibration Value Register (Adcx_Clm1)
788
ADC Minus-Side General Calibration Value Register (Adcx_Clm0)
789
Functional Description
789
Clock Select and Divide Control
790
Voltage Reference Selection
791
Hardware Trigger and Channel Selects
791
Conversion Control
792
Automatic Compare Function
800
Calibration Function
801
User-Defined Offset Function
803
Temperature Sensor
804
MCU Wait Mode Operation
805
MCU Normal Stop Mode Operation
805
MCU Low-Power Stop Mode Operation
806
Initialization Information
807
ADC Module Initialization Example
807
Application Information
809
External Pins and Routing
809
Sources of Error
811
Introduction
817
Chapter 35
817
CMP Features
817
6-Bit DAC Key Features
818
ANMUX Key Features
818
CMP, DAC and ANMUX Diagram
819
CMP Block Diagram
820
Memory Map/Register Definitions
822
CMP Control Register 0 (Cmpx_Cr0)
822
CMP Control Register 1 (Cmpx_Cr1)
823
CMP Filter Period Register (Cmpx_Fpr)
825
CMP Status and Control Register (Cmpx_Scr)
825
DAC Control Register (Cmpx_Daccr)
826
MUX Control Register (Cmpx_Muxcr)
827
Functional Description
828
CMP Functional Modes
828
Power Modes
837
Startup and Operation
838
Low-Pass Filter
839
CMP Interrupts
841
DMA Support
841
CMP Asynchronous DMA Support
842
Digital-To-Analog Converter
843
DAC Functional Description
843
Voltage Reference Source Select
843
DAC Resets
844
DAC Clocks
844
DAC Interrupts
844
Chapter 36
845
Introduction
845
Features
845
Block Diagram
845
Memory Map/Register Definition
846
DAC Data Low Register (Dacx_Datnl)
849
DAC Data High Register (Dacx_Datnh)
849
DAC Status Register (Dacx_Sr)
850
DAC Control Register (Dacx_C0)
851
DAC Control Register 1 (Dacx_C1)
852
DAC Control Register 2 (Dacx_C2)
853
Functional Description
853
DAC Data Buffer Operation
853
DMA Operation
855
Resets
855
Low-Power Mode Operation
855
Introduction
857
Overview
858
Features
858
Chapter 37 Voltage Reference (VREFV1)
859
Modes of Operation
859
VREF Signal Descriptions
859
Memory Map and Register Definition
860
VREF Trim Register (VREF_TRM)
860
VREF Status and Control Register (VREF_SC)
861
Functional Description
862
Voltage Reference Disabled, SC[VREFEN] = 0
863
Voltage Reference Enabled, SC[VREFEN] = 1
863
Internal Voltage Regulator
864
Initialization/Application Information
865
Introduction
867
Features
867
Implementation
868
Chapter 38 Programmable Delay Block (PDB)
869
Back-To-Back Acknowledgment Connections
869
DAC External Trigger Input Connections
869
Block Diagram
869
Modes of Operation
871
PDB Signal Descriptions
871
Memory Map and Register Definition
871
Status and Control Register (Pdbx_Sc)
873
Modulus Register (Pdbx_Mod)
876
Counter Register (Pdbx_Cnt)
876
Interrupt Delay Register (Pdbx_Idly)
877
Channel N Control Register 1 (Pdbx_Chnc1)
877
Channel N Status Register (Pdbx_Chns)
878
Channel N Delay 0 Register (Pdbx_Chndly0)
879
Channel N Delay 1 Register (Pdbx_Chndly1)
880
DAC Interval Trigger N Control Register (Pdbx_Dacintcn)
880
DAC Interval N Register (Pdbx_Dacintn)
881
Pulse-Out N Enable Register (Pdbx_Poen)
882
Pulse-Out N Delay Register (Pdbx_Pondly)
882
Functional Description
883
PDB Pre-Trigger and Trigger Outputs
883
PDB Trigger Input Source Selection
885
Pulse-Out's
885
Updating the Delay Registers
886
Interrupts
888
Dma
888
Application Information
888
Impact of Using the Prescaler and Multiplication Factor on Timing Resolution
888
Chapter 39 Flextimer Module (FTM)
891
Introduction
891
Flextimer Philosophy
891
Features
892
Modes of Operation
893
Block Diagram
894
FTM Signal Descriptions
896
Memory Map and Register Definition
896
Memory Map
896
Register Descriptions
897
Status and Control (Ftmx_Sc)
903
Counter (Ftmx_Cnt)
904
Modulo (Ftmx_Mod)
905
Channel (N) Status and Control (Ftmx_Cnsc)
906
Channel (N) Value (Ftmx_Cnv)
909
Counter Initial Value (Ftmx_Cntin)
909
Capture and Compare Status (Ftmx_Status)
910
Features Mode Selection (Ftmx_Mode)
912
Synchronization (Ftmx_Sync)
914
Initial State for Channels Output (Ftmx_Outinit)
916
Output Mask (Ftmx_Outmask)
917
Function for Linked Channels (Ftmx_Combine)
919
Deadtime Insertion Control (Ftmx_Deadtime)
924
FTM External Trigger (Ftmx_Exttrig)
925
Channels Polarity (Ftmx_Pol)
927
Fault Mode Status (Ftmx_Fms)
929
Input Capture Filter Control (Ftmx_Filter)
931
Fault Control (Ftmx_Fltctrl)
932
Quadrature Decoder Control and Status (Ftmx_Qdctrl)
935
Configuration (Ftmx_Conf)
937
FTM Fault Input Polarity (Ftmx_Fltpol)
938
Synchronization Configuration (Ftmx_Synconf)
939
FTM Inverting Control (Ftmx_Invctrl)
941
FTM Software Output Control (Ftmx_Swoctrl)
942
FTM PWM Load (Ftmx_Pwmload)
945
Functional Description
946
Clock Source
947
Prescaler
948
Counter
948
Input Capture Mode
954
Output Compare Mode
958
Edge-Aligned PWM (EPWM) Mode
959
Center-Aligned PWM (CPWM) Mode
961
Combine Mode
963
Complementary Mode
970
Registers Updated from Write Buffers
971
PWM Synchronization
973
Inverting
989
Software Output Control
990
Deadtime Insertion
992
Output Mask
995
Fault Control
996
Polarity Control
999
Initialization
1000
Features Priority
1000
Channel Trigger Output
1001
Initialization Trigger
1002
Capture Test Mode
1005
Dma
1006
Dual Edge Capture Mode
1006
Quadrature Decoder Mode
1014
BDM Mode
1019
Intermediate Load
1020
Global Time Base (GTB)
1022
Reset Overview
1024
FTM Interrupts
1025
Timer Overflow Interrupt
1026
Channel (N) Interrupt
1026
Fault Interrupt
1026
Initialization Procedure
1026
Chapter 40 Periodic Interrupt Timer (PIT)
1029
Introduction
1029
Block Diagram
1029
Features
1030
Signal Description
1030
Memory Map/Register Description
1031
PIT Module Control Register (PIT_MCR)
1031
Timer Load Value Register (Pit_Ldvaln)
1033
Current Timer Value Register (Pit_Cvaln)
1033
Timer Control Register (Pit_Tctrln)
1034
Timer Flag Register (Pit_Tflgn)
1034
Functional Description
1035
General Operation
1035
Interrupts
1037
Chained Timers
1037
Initialization and Application Information
1037
Example Configuration for Chained Timers
1038
Chapter 41 Low-Power Timer (LPTMR)
1041
Introduction
1041
Features
1041
Modes of Operation
1041
LPTMR Signal Descriptions
1042
Detailed Signal Descriptions
1042
Memory Map and Register Definition
1042
Low Power Timer Control Status Register (Lptmrx_Csr)
1043
Low Power Timer Prescale Register (Lptmrx_Psr)
1044
Low Power Timer Compare Register (Lptmrx_Cmr)
1046
Low Power Timer Counter Register (Lptmrx_Cnr)
1046
Functional Description
1047
LPTMR Power and Reset
1047
LPTMR Clocking
1047
LPTMR Prescaler/Glitch Filter
1047
LPTMR Compare
1049
LPTMR Counter
1049
LPTMR Hardware Trigger
1050
LPTMR Interrupt
1050
Introduction
1051
Chapter 42
1051
Features
1051
Modes of Operation
1051
RTC Signal Descriptions
1052
Register Definition
1053
RTC Time Seconds Register (RTC_TSR)
1053
RTC Time Prescaler Register (RTC_TPR)
1054
RTC Time Alarm Register (RTC_TAR)
1054
RTC Time Compensation Register (RTC_TCR)
1055
RTC Control Register (RTC_CR)
1056
RTC Status Register (RTC_SR)
1058
RTC Lock Register (RTC_LR)
1059
RTC Interrupt Enable Register (RTC_IER)
1060
RTC Write Access Register (RTC_WAR)
1061
RTC Read Access Register (RTC_RAR)
1062
Functional Description
1064
Power, Clocking, and Reset
1064
Time Counter
1065
Compensation
1066
Time Alarm
1066
Update Mode
1067
Register Lock
1067
Access Control
1067
Interrupt
1067
Introduction
1069
References
1069
Usb
1070
USB On-The-Go
1071
USBFS Features
1072
Functional Description
1072
Data Structures
1072
On-Chip Transceiver Required External Components
1073
Programmers Interface
1075
Buffer Descriptor Table
1075
RX Vs. TX as a USB Peripheral Device or USB Host
1076
Addressing BDT Entries
1077
Buffer Descriptors (Bds)
1078
USB Transaction
1080
Memory Map/Register Definitions
1082
Peripheral ID Register (Usbx_Perid)
1084
Peripheral ID Complement Register (Usbx_Idcomp)
1085
Peripheral Revision Register (Usbx_Rev)
1085
Peripheral Additional Info Register (Usbx_Addinfo)
1086
OTG Interrupt Status Register (Usbx_Otgistat)
1086
OTG Interrupt Control Register (Usbx_Otgicr)
1087
OTG Status Register (Usbx_Otgstat)
1088
OTG Control Register (Usbx_Otgctl)
1089
Interrupt Status Register (Usbx_Istat)
1090
Interrupt Enable Register (Usbx_Inten)
1091
Error Interrupt Status Register (Usbx_Errstat)
1093
Error Interrupt Enable Register (Usbx_Erren)
1094
Status Register (Usbx_Stat)
1095
Control Register (Usbx_Ctl)
1096
Address Register (Usbx_Addr)
1097
BDT Page Register 1 (Usbx_Bdtpage1)
1098
Frame Number Register Low (Usbx_Frmnuml)
1098
Frame Number Register High (Usbx_Frmnumh)
1099
Token Register (Usbx_Token)
1099
SOF Threshold Register (Usbx_Softhld)
1100
BDT Page Register 2 (Usbx_Bdtpage2)
1101
BDT Page Register 3 (Usbx_Bdtpage3)
1101
Endpoint Control Register (Usbx_Endptn)
1102
USB Control Register (Usbx_Usbctrl)
1103
USB OTG Observe Register (Usbx_Observe)
1104
USB OTG Control Register (Usbx_Control)
1104
USB Transceiver Control Register 0 (Usbx_Usbtrc0)
1105
Frame Adjust Register (Usbx_Usbfrmadjust)
1106
USB Clock Recovery Control (Usbx_Clk_Recover_Ctrl)
1107
IRC48M Oscillator Enable Register (Usbx_Clk_Recover_Irc_En)
1108
Clock Recovery Combined Interrupt Enable (Usbx_Clk_Recover_Int_En)
1109
Clock Recovery Separated Interrupt Status (Usbx_Clk_Recover_Int_Status)
1109
OTG and Host Mode Operation
1110
Host Mode Operation Examples
1110
On-The-Go Operation
1113
OTG Dual Role a Device Operation
1114
OTG Dual Role B Device Operation
1115
Device Mode IRC48 Operation
1117
Modes of Operation
1121
USB Voltage Regulator Module Signal Descriptions
1121
Introduction
1123
Chapter 45
1123
Block Diagram
1123
Features
1124
Interface Configurations
1126
Modes of Operation
1126
Module Signal Descriptions
1128
PCS0/SS-Peripheral Chip Select/Slave Select
1128
PCS1-PCS3-Peripheral Chip Selects 1-3
1129
PCS4-Peripheral Chip Select 4
1129
PCS5/PCSS-Peripheral Chip Select 5/Peripheral Chip Select Strobe
1129
SCK-Serial Clock
1129
SIN-Serial Input
1129
SOUT-Serial Output
1130
Memory Map/Register Definition
1130
Module Configuration Register (Spix_Mcr)
1132
Transfer Count Register (Spix_Tcr)
1135
Clock and Transfer Attributes Register (in Master Mode) (Spix_Ctarn)
1136
Clock and Transfer Attributes Register (in Slave Mode) (Spix_Ctarn_Slave)
1140
Status Register (Spix_Sr)
1142
Dma/Interrupt Request Select and Enable Register (Spix_Rser)
1145
PUSH TX FIFO Register in Master Mode (Spix_Pushr)
1147
PUSH TX FIFO Register in Slave Mode (Spix_Pushr_Slave)
1149
POP RX FIFO Register (Spix_Popr)
1149
Transmit FIFO Registers (Spix_Txfrn)
1150
Receive FIFO Registers (Spix_Rxfrn)
1150
Functional Description
1151
Start and Stop of Module Transfers
1152
Serial Peripheral Interface (SPI) Configuration
1152
Module Baud Rate and Clock Delay Generation
1156
Transfer Formats
1160
Continuous Serial Communications Clock
1169
Slave Mode Operation Constraints
1171
Interrupts/Dma Requests
1171
Power Saving Features
1173
Initialization/Application Information
1174
How to Manage Queues
1175
Switching Master and Slave Mode
1175
Initializing Module in Master/Slave Modes
1176
Baud Rate Settings
1176
Delay Settings
1177
Calculation of FIFO Pointer Addresses
1178
Chapter 46 Inter-Integrated Circuit (I2C)
1181
Introduction
1181
Features
1181
Modes of Operation
1182
Block Diagram
1182
I2C Signal Descriptions
1183
Memory Map/Register Definition
1184
I2C Address Register 1 (I2Cx_A1)
1185
I2C Frequency Divider Register (I2Cx_F)
1185
I2C Control Register 1 (I2Cx_C1)
1186
I2C Status Register (I2Cx_S)
1188
I2C Data I/O Register (I2Cx_D)
1190
I2C Control Register 2 (I2Cx_C2)
1190
I2C Programmable Input Glitch Filter Register (I2Cx_Flt)
1191
I2C Range Address Register (I2Cx_Ra)
1193
I2C Smbus Control and Status Register (I2Cx_Smb)
1193
I2C Address Register 2 (I2Cx_A2)
1195
I2C SCL Low Timeout Register High (I2Cx_Slth)
1195
I2C SCL Low Timeout Register Low (I2Cx_Sltl)
1196
Functional Description
1196
I2C Protocol
1196
10-Bit Address
1201
Address Matching
1203
System Management Bus Specification
1204
Resets
1206
Interrupts
1207
Programmable Input Glitch Filter
1209
Address Matching Wake-Up
1209
DMA Support
1210
Initialization/Application Information
1211
Chapter 47 Universal Asynchronous Receiver/Transmitter (UART)
1215
Introduction
1215
Features
1215
Modes of Operation
1217
UART Signal Descriptions
1218
Detailed Signal Descriptions
1218
Memory Map and Registers
1219
UART Baud Rate Registers: High (Uartx_Bdh)
1224
UART Baud Rate Registers: Low (Uartx_Bdl)
1225
UART Control Register 1 (Uartx_C1)
1226
UART Control Register 2 (Uartx_C2)
1227
UART Status Register 1 (Uartx_S1)
1229
UART Status Register 2 (Uartx_S2)
1232
UART Control Register 3 (Uartx_C3)
1234
UART Data Register (Uartx_D)
1235
UART Match Address Registers 1 (Uartx_Ma1)
1236
UART Match Address Registers 2 (Uartx_Ma2)
1237
UART Control Register 4 (Uartx_C4)
1237
UART Control Register 5 (Uartx_C5)
1238
UART Extended Data Register (Uartx_Ed)
1239
UART Modem Register (Uartx_Modem)
1240
UART Infrared Register (Uartx_Ir)
1241
UART FIFO Parameters (Uartx_Pfifo)
1242
UART FIFO Control Register (Uartx_Cfifo)
1243
UART FIFO Status Register (Uartx_Sfifo)
1244
UART FIFO Transmit Watermark (Uartx_Twfifo)
1245
UART FIFO Transmit Count (Uartx_Tcfifo)
1246
UART FIFO Receive Watermark (Uartx_Rwfifo)
1246
UART FIFO Receive Count (Uartx_Rcfifo)
1247
UART 7816 Control Register (Uartx_C7816)
1247
UART 7816 Interrupt Enable Register (Uartx_Ie7816)
1249
UART 7816 Interrupt Status Register (Uartx_Is7816)
1250
UART 7816 Wait Parameter Register (Uartx_Wp7816)
1252
UART 7816 Wait N Register (Uartx_Wn7816)
1252
UART 7816 Wait FD Register (Uartx_Wf7816)
1253
UART 7816 Error Threshold Register (Uartx_Et7816)
1253
UART 7816 Transmit Length Register (Uartx_Tl7816)
1254
UART 7816 ATR Duration Timer Register a (Uartx_Ap7816A_T0)
1254
UART 7816 ATR Duration Timer Register B (Uartx_Ap7816B_T0)
1255
UART 7816 Wait Parameter Register a (Uartx_Wp7816A_T0)
1256
UART 7816 Wait Parameter Register a (Uartx_Wp7816A_T1)
1256
UART 7816 Wait Parameter Register B (Uartx_Wp7816B_T0)
1257
UART 7816 Wait Parameter Register B (Uartx_Wp7816B_T1)
1257
UART 7816 Wait and Guard Parameter Register (Uartx_Wgp7816_T1)
1258
UART 7816 Wait Parameter Register C (Uartx_Wp7816C_T1)
1258
Functional Description
1259
Transmitter
1259
Receiver
1265
Baud Rate Generation
1279
Data Format (Non ISO-7816)
1281
Single-Wire Operation
1284
Loop Operation
1285
ISO-7816/Smartcard Support
1285
Infrared Interface
1291
Reset
1292
System Level Interrupt Sources
1292
RXEDGIF Description
1292
DMA Operation
1293
Application Information
1294
Transmit/Receive Data Buffer Operation
1294
Initialization Sequence
1294
Initialization Sequence (Non ISO-7816)
1296
Overrun (OR) Flag Implications
1297
Overrun NACK Considerations
1298
Match Address Registers
1299
Modem Feature
1299
Irda Minimum Pulse Width
1300
Clearing 7816 Wait Timer (WT, BWT, CWT) Interrupts
1300
Legacy and Reverse Compatibility Considerations
1301
Chapter 48 Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
1303
Introduction
1303
Features
1303
Modes of Operation
1304
Signal Descriptions
1304
Block Diagram
1305
Register Definition
1306
LPUART Baud Rate Register (Lpuartx_Baud)
1307
LPUART Status Register (Lpuartx_Stat)
1309
LPUART Control Register (Lpuartx_Ctrl)
1313
LPUART Data Register (Lpuartx_Data)
1318
LPUART Match Address Register (Lpuartx_Match)
1320
LPUART Modem Irda Register (Lpuartx_Modir)
1320
Functional Description
1322
Baud Rate Generation
1322
Transmitter Functional Description
1323
Receiver Functional Description
1326
Additional LPUART Functions
1332
Infrared Interface
1334
Interrupts and Status Flags
1335
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
1337
Introduction
1337
Features
1337
Block Diagram
1338
Modes of Operation
1338
External Signals
1339
Memory Map and Register Definition
1340
SAI Transmit Control Register (I2Sx_Tcsr)
1341
SAI Transmit Configuration 1 Register (I2Sx_Tcr1)
1344
SAI Transmit Configuration 2 Register (I2Sx_Tcr2)
1345
SAI Transmit Configuration 3 Register (I2Sx_Tcr3)
1346
SAI Transmit Configuration 4 Register (I2Sx_Tcr4)
1347
SAI Transmit Configuration 5 Register (I2Sx_Tcr5)
1349
SAI Transmit Data Register (I2Sx_Tdrn)
1350
SAI Transmit FIFO Register (I2Sx_Tfrn)
1350
SAI Transmit Mask Register (I2Sx_Tmr)
1351
SAI Receive Control Register (I2Sx_Rcsr)
1352
SAI Receive Configuration 1 Register (I2Sx_Rcr1)
1355
SAI Receive Configuration 2 Register (I2Sx_Rcr2)
1355
SAI Receive Configuration 3 Register (I2Sx_Rcr3)
1357
SAI Receive Configuration 4 Register (I2Sx_Rcr4)
1358
SAI Receive Configuration 5 Register (I2Sx_Rcr5)
1360
SAI Receive Data Register (I2Sx_Rdrn)
1360
SAI Receive FIFO Register (I2Sx_Rfrn)
1361
SAI Receive Mask Register (I2Sx_Rmr)
1361
SAI MCLK Control Register (I2Sx_Mcr)
1362
SAI MCLK Divide Register (I2Sx_Mdr)
1363
Functional Description
1364
SAI Clocking
1364
SAI Resets
1366
Synchronous Modes
1367
Frame Sync Configuration
1367
Data FIFO
1368
Word Mask Register
1371
Interrupts and DMA Requests
1371
Introduction
1375
Features
1375
Modes of Operation
1375
Chapter 50 General-Purpose Input/Output (GPIO)
1376
GPIO Signal Descriptions
1376
Memory Map and Register Definition
1377
Port Data Output Register (Gpiox_Pdor)
1378
Port Set Output Register (Gpiox_Psor)
1379
Port Clear Output Register (Gpiox_Pcor)
1380
Port Toggle Output Register (Gpiox_Ptor)
1380
Port Data Input Register (Gpiox_Pdir)
1381
Port Data Direction Register (Gpiox_Pddr)
1381
Functional Description
1382
General-Purpose Input
1382
General-Purpose Output
1382
Chapter 51 JTAG Controller (JTAGC)
1383
Introduction
1383
Block Diagram
1383
Features
1384
Modes of Operation
1384
External Signal Description
1386
TCK-Test Clock Input
1386
TDI-Test Data Input
1386
TDO-Test Data Output
1386
TMS-Test Mode Select
1386
Register Description
1387
Instruction Register
1387
Bypass Register
1387
Device Identification Register
1387
Boundary Scan Register
1388
Functional Description
1389
JTAGC Reset Configuration
1389
IEEE 1149.1-2001 (JTAG) Test Access Port
1389
TAP Controller State Machine
1389
JTAGC Block Instructions
1391
Boundary Scan
1394
Initialization/Application Information
1394
4
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NXP Semiconductors K22F series Specifications
General
Brand
NXP Semiconductors
Model
K22F series
Category
Controller
Language
English
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