64
MAP
BGA
64
LQFP
80
WLC
SP
88
QFN
100
LQFP
121
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EZPORT
— — — — 33 H6 PTE26/
CLKOUT3
2K
DISABLE
D
PTE26/
CLKOUT3
2K
RTC_
CLKOUT
USB_
CLKIN
D3 22 F7 27 34 J6 PTA0 JTAG_
TCLK/
SWD_
CLK/
EZP_CLK
PTA0 UART0_
CTS_b
FTM0_
CH5
JTAG_
TCLK/
SWD_CLK
EZP_CLK
D4 23 F6 28 35 H8 PTA1 JTAG_
TDI/
EZP_DI
PTA1 UART0_
RX
FTM0_
CH6
JTAG_TDI EZP_DI
E5 24 F5 29 36 J7 PTA2 JTAG_
TDO/
TRACE_
SWO/
EZP_DO
PTA2 UART0_
TX
FTM0_
CH7
JTAG_
TDO/
TRACE_
SWO
EZP_DO
D5 25 F4 30 37 H9 PTA3 JTAG_
TMS/
SWD_DIO
PTA3 UART0_
RTS_b
FTM0_
CH0
JTAG_
TMS/
SWD_DIO
G5 26 G6 31 38 J8 PTA4/
LLWU_P3
NMI_b/
EZP_CS_
b
PTA4/
LLWU_P3
FTM0_
CH1
NMI_b EZP_CS_
b
F5 27 H5 32 39 K7 PTA5 DISABLE
D
PTA5 USB_
CLKIN
FTM0_
CH2
I2S0_TX_
BCLK
JTAG_
TRST_b
— — — 33 40 E5 VDD VDD VDD
— — — 34 41 G3 VSS VSS VSS
— — — — — J9 PTA10 DISABLE
D
PTA10 FTM2_
CH0
FTM2_
QD_PHA
— — — — — J4 PTA11 DISABLE
D
PTA11 FTM2_
CH1
FTM2_
QD_PHB
H6 28 H6 35 42 K8 PTA12 DISABLE
D
PTA12 FTM1_
CH0
I2S0_
TXD0
FTM1_
QD_PHA
G6 29 H4 36 43 L8 PTA13/
LLWU_P4
DISABLE
D
PTA13/
LLWU_P4
FTM1_
CH1
I2S0_TX_
FS
FTM1_
QD_PHB
— — G5 37 44 K9 PTA14 DISABLE
D
PTA14 SPI0_
PCS0
UART0_
TX
I2S0_RX_
BCLK
— — G4 38 45 L9 PTA15 DISABLE
D
PTA15 SPI0_SCK UART0_
RX
I2S0_
RXD0
— — H3 39 46 J10 PTA16 DISABLE
D
PTA16 SPI0_
SOUT
UART0_
CTS_b
I2S0_RX_
FS
— — G3 40 47 H10 PTA17 ADC1_
SE17
ADC1_
SE17
PTA17 SPI0_SIN UART0_
RTS_b
I2S0_
MCLK
G7 30 E6 41 48 L10 VDD VDD VDD
H7 31 G2 42 49 K10 VSS VSS VSS
H8 32 H2 43 50 L11 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_
FLT2
FTM_
CLKIN0
G8 33 H1 44 51 K11 PTA19 XTAL0 XTAL0 PTA19 FTM1_
FLT0
FTM_
CLKIN1
LPTMR0_
ALT1
Pinout
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
218 NXP Semiconductors
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