NXP Semiconductors K22F series - Page 26

Section number Title Page
33.3.2 RNGA Status Register (RNG_SR).............................................................................................................. 755
33.3.3 RNGA Entropy Register (RNG_ER)...........................................................................................................757
33.3.4 RNGA Output Register (RNG_OR)............................................................................................................ 757
33.4 Functional description...................................................................................................................................................758
33.4.1 Output (OR) register.................................................................................................................................... 758
33.4.2 Core engine / control logic...........................................................................................................................758
33.5 Initialization/application information........................................................................................................................... 759
Chapter 34
Analog-to-Digital Converter (ADC)
34.1 Introduction...................................................................................................................................................................761
34.1.1 Features........................................................................................................................................................ 761
34.1.2 Block diagram..............................................................................................................................................762
34.2 ADC signal descriptions............................................................................................................................................... 764
34.2.1 Analog Power (VDDA)............................................................................................................................... 765
34.2.2 Analog Ground (VSSA)...............................................................................................................................765
34.2.3 Voltage Reference Select.............................................................................................................................765
34.2.4 Analog Channel Inputs (ADx)..................................................................................................................... 766
34.2.5 Differential Analog Channel Inputs (DADx)...............................................................................................766
34.3 Memory map and register definitions...........................................................................................................................766
34.3.1
ADC Status and Control Registers 1 (ADCx_SC1n)...................................................................................768
34.3.2
ADC Configuration Register 1 (ADCx_CFG1)...........................................................................................772
34.3.3
ADC Configuration Register 2 (ADCx_CFG2)...........................................................................................773
34.3.4
ADC Data Result Register (ADCx_Rn).......................................................................................................774
34.3.5
Compare Value Registers (ADCx_CVn)..................................................................................................... 776
34.3.6
Status and Control Register 2 (ADCx_SC2)................................................................................................777
34.3.7
Status and Control Register 3 (ADCx_SC3)................................................................................................779
34.3.8
ADC Offset Correction Register (ADCx_OFS)...........................................................................................780
34.3.9
ADC Plus-Side Gain Register (ADCx_PG).................................................................................................781
34.3.10
ADC Minus-Side Gain Register (ADCx_MG)............................................................................................ 781
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
26 NXP Semiconductors