NXP Semiconductors K22F series - Page 283

SIM_SCGC6 field descriptions (continued)
Field Description
12
SPI0
SPI0 Clock Gate Control
This bit controls the clock gate to the SPI0 module.
0 Clock disabled
1 Clock enabled
11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10
LPUART0
LPUART0 Clock Gate Control
This bit controls the clock gate to the LPUART0 module.
0 Clock disabled
1 Clock enabled
9
RNGA
RNGA Clock Gate Control
This bit controls the clock gate to the RNGA module.
8
DAC1
DAC1 Clock Gate Control
This bit controls the clock gate to the DAC1 module.
0 Clock disabled
1 Clock enabled
7
ADC1
ADC1 Clock Gate Control
This bit controls the clock gate to the ADC1 module.
0 Clock disabled
1 Clock enabled
6
FTM3
FTM3 Clock Gate Control
This bit controls the clock gate to the FTM3 module.
0 Clock disabled
1 Clock enabled
5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1
DMAMUX
DMA Mux Clock Gate Control
This bit controls the clock gate to the DMA Mux module.
0 Clock disabled
1 Clock enabled
0
FTF
Flash Memory Clock Gate Control
This bit controls the clock gate to the flash memory. Flash reads are still supported while the flash memory
is clock gated, but entry into low power modes and HSRUN mode is blocked.
Table continues on the next page...
Chapter 12 System Integration Module (SIM)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 283