DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_9008
TCD Minor Byte Count (Minor Loop Mapping Disabled)
(DMA_TCD0_NBYTES_MLNO)
32 R/W Undefined 22.3.25/471
4000_9008
TCD Signed Minor Loop Offset (Minor Loop Mapping
Enabled and Offset Disabled)
(DMA_TCD0_NBYTES_MLOFFNO)
32 R/W Undefined 22.3.26/472
4000_9008
TCD Signed Minor Loop Offset (Minor Loop Mapping and
Offset Enabled) (DMA_TCD0_NBYTES_MLOFFYES)
32 R/W Undefined 22.3.27/473
4000_900C
TCD Last Source Address Adjustment
(DMA_TCD0_SLAST)
32 R/W Undefined 22.3.28/474
4000_9010 TCD Destination Address (DMA_TCD0_DADDR) 32 R/W Undefined 22.3.29/475
4000_9014
TCD Signed Destination Address Offset
(DMA_TCD0_DOFF)
16 R/W Undefined 22.3.30/475
4000_9016
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD0_CITER_ELINKYES)
16 R/W Undefined 22.3.31/476
4000_9016 DMA_TCD0_CITER_ELINKNO 16 R/W Undefined 22.3.32/477
4000_9018
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD0_DLASTSGA)
32 R/W Undefined 22.3.33/478
4000_901C TCD Control and Status (DMA_TCD0_CSR) 16 R/W Undefined 22.3.34/479
4000_901E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD0_BITER_ELINKYES)
16 R/W Undefined 22.3.35/481
4000_901E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled) (DMA_TCD0_BITER_ELINKNO)
16 R/W Undefined 22.3.36/482
4000_9020 TCD Source Address (DMA_TCD1_SADDR) 32 R/W Undefined 22.3.22/469
4000_9024 TCD Signed Source Address Offset (DMA_TCD1_SOFF) 16 R/W Undefined 22.3.23/469
4000_9026 TCD Transfer Attributes (DMA_TCD1_ATTR) 16 R/W Undefined 22.3.24/470
4000_9028
TCD Minor Byte Count (Minor Loop Mapping Disabled)
(DMA_TCD1_NBYTES_MLNO)
32 R/W Undefined 22.3.25/471
4000_9028
TCD Signed Minor Loop Offset (Minor Loop Mapping
Enabled and Offset Disabled)
(DMA_TCD1_NBYTES_MLOFFNO)
32 R/W Undefined 22.3.26/472
4000_9028
TCD Signed Minor Loop Offset (Minor Loop Mapping and
Offset Enabled) (DMA_TCD1_NBYTES_MLOFFYES)
32 R/W Undefined 22.3.27/473
4000_902C
TCD Last Source Address Adjustment
(DMA_TCD1_SLAST)
32 R/W Undefined 22.3.28/474
4000_9030 TCD Destination Address (DMA_TCD1_DADDR) 32 R/W Undefined 22.3.29/475
4000_9034
TCD Signed Destination Address Offset
(DMA_TCD1_DOFF)
16 R/W Undefined 22.3.30/475
4000_9036
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD1_CITER_ELINKYES)
16 R/W Undefined 22.3.31/476
4000_9036 DMA_TCD1_CITER_ELINKNO 16 R/W Undefined 22.3.32/477
4000_9038
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD1_DLASTSGA)
32 R/W Undefined 22.3.33/478
Table continues on the next page...
Memory map/register definition
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
432 NXP Semiconductors