DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_906C
TCD Last Source Address Adjustment
(DMA_TCD3_SLAST)
32 R/W Undefined 22.3.28/474
4000_9070 TCD Destination Address (DMA_TCD3_DADDR) 32 R/W Undefined 22.3.29/475
4000_9074
TCD Signed Destination Address Offset
(DMA_TCD3_DOFF)
16 R/W Undefined 22.3.30/475
4000_9076
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD3_CITER_ELINKYES)
16 R/W Undefined 22.3.31/476
4000_9076 DMA_TCD3_CITER_ELINKNO 16 R/W Undefined 22.3.32/477
4000_9078
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD3_DLASTSGA)
32 R/W Undefined 22.3.33/478
4000_907C TCD Control and Status (DMA_TCD3_CSR) 16 R/W Undefined 22.3.34/479
4000_907E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD3_BITER_ELINKYES)
16 R/W Undefined 22.3.35/481
4000_907E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled) (DMA_TCD3_BITER_ELINKNO)
16 R/W Undefined 22.3.36/482
4000_9080 TCD Source Address (DMA_TCD4_SADDR) 32 R/W Undefined 22.3.22/469
4000_9084 TCD Signed Source Address Offset (DMA_TCD4_SOFF) 16 R/W Undefined 22.3.23/469
4000_9086 TCD Transfer Attributes (DMA_TCD4_ATTR) 16 R/W Undefined 22.3.24/470
4000_9088
TCD Minor Byte Count (Minor Loop Mapping Disabled)
(DMA_TCD4_NBYTES_MLNO)
32 R/W Undefined 22.3.25/471
4000_9088
TCD Signed Minor Loop Offset (Minor Loop Mapping
Enabled and Offset Disabled)
(DMA_TCD4_NBYTES_MLOFFNO)
32 R/W Undefined 22.3.26/472
4000_9088
TCD Signed Minor Loop Offset (Minor Loop Mapping and
Offset Enabled) (DMA_TCD4_NBYTES_MLOFFYES)
32 R/W Undefined 22.3.27/473
4000_908C
TCD Last Source Address Adjustment
(DMA_TCD4_SLAST)
32 R/W Undefined 22.3.28/474
4000_9090 TCD Destination Address (DMA_TCD4_DADDR) 32 R/W Undefined 22.3.29/475
4000_9094
TCD Signed Destination Address Offset
(DMA_TCD4_DOFF)
16 R/W Undefined 22.3.30/475
4000_9096
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD4_CITER_ELINKYES)
16 R/W Undefined 22.3.31/476
4000_9096 DMA_TCD4_CITER_ELINKNO 16 R/W Undefined 22.3.32/477
4000_9098
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD4_DLASTSGA)
32 R/W Undefined 22.3.33/478
4000_909C TCD Control and Status (DMA_TCD4_CSR) 16 R/W Undefined 22.3.34/479
4000_909E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD4_BITER_ELINKYES)
16 R/W Undefined 22.3.35/481
4000_909E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled) (DMA_TCD4_BITER_ELINKNO)
16 R/W Undefined 22.3.36/482
4000_90A0 TCD Source Address (DMA_TCD5_SADDR) 32 R/W Undefined 22.3.22/469
Table continues on the next page...
Memory map/register definition
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
434 NXP Semiconductors