to test the TCDn_CSR[START] bit and the TCDn_CSR[ACTIVE] bit. The minor-loop-
complete condition is indicated by both bits reading zero after the TCDn_CSR[START]
was set. Polling the TCDn_CSR[ACTIVE] bit may be inconclusive, because the active
status may be missed if the channel execution is short in duration.
The TCD status bits execute the following sequence for a software activated channel:
Stage
TCDn_CSR bits
State
START ACTIVE DONE
1 1 0 0 Channel service request via software
2 0 1 0 Channel is executing
3a 0 0 0 Channel has completed the minor loop and is idle
3b 0 0 1 Channel has completed the major loop and is idle
The best method to test for minor-loop completion when using hardware, that is,
peripheral, initiated service requests is to read the TCDn_CITER field and test for a
change. The hardware request and acknowledge handshake signals are not visible in the
programmer's model.
The TCD status bits execute the following sequence for a hardware-activated channel:
Stage
TCDn_CSR bits
State
START ACTIVE DONE
1 0 0 0
Channel service request via hardware (peripheral
request asserted)
2 0 1 0 Channel is executing
3a 0 0 0 Channel has completed the minor loop and is idle
3b 0 0 1 Channel has completed the major loop and is idle
For both activation types, the major-loop-complete status is explicitly indicated via the
TCDn_CSR[DONE] bit.
The TCDn_CSR[START] bit is cleared automatically when the channel begins execution
regardless of how the channel activates.
22.5.5.2
Reading the transfer descriptors of active channels
The eDMA reads back the true TCDn_SADDR, TCDn_DADDR, and TCDn_NBYTES
values if read while a channel executes. The true values of the SADDR, DADDR, and
NBYTES are the values the eDMA engine currently uses in its internal register file and
not the values in the TCD local memory for that channel. The addresses, SADDR and
Chapter 22 Enhanced Direct Memory Access (eDMA)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 501
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