NOTE
• During exits from LLS or VLPS when the MCG is in PEE
mode, the MCG will reset to PBE clock mode and the
C1[CLKS] and S[CLKST] will automatically be set to
2’b10.
• If entering Normal Stop mode when the MCG is in PEE
mode with PLLSTEN=0, the MCG will reset to PBE clock
mode and C1[CLKS] and S[CLKST] will automatically be
set to 2’b10.
25.4.1.1 MCG modes of operation
The MCG operates in one of the following modes.
Note
The MCG restricts transitions between modes. For the
permitted transitions, see Figure 25-2.
Table 25-3. MCG modes of operation
Mode Description
FLL Engaged Internal
(FEI)
FLL engaged internal (FEI) is the default mode of operation and is entered when all the following
condtions occur:
• 00 is written to C1[CLKS].
• 1 is written to C1[IREFS].
• 0 is written to C6[PLLS].
In FEI mode, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by the 32
kHz Internal Reference Clock (IRC). The FLL loop will lock the DCO frequency to the FLL factor, as
selected by C4[DRST_DRS] and C4[DMX32] bits, times the internal reference frequency. See the
C4[DMX32] bit description for more details. In FEI mode, the PLL is disabled in a low-power state
unless C5[PLLCLKEN] is set .
FLL Engaged External
(FEE)
FLL engaged external (FEE) mode is entered when all the following conditions occur:
• 00 is written to C1[CLKS].
• 0 is written to C1[IREFS].
• C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25
kHz to 39.0625 kHz
• 0 is written to C6[PLLS].
Table continues on the next page...
Functional description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
558 NXP Semiconductors
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