NXP Semiconductors K22F series - Page 571

C2 = 0x1C
(S[LP]=0)
IN
BLPE MODE ?
C6 = 0x40
C2 = 0x1C
START
IN FEI MODE
NO
NO
NO
NO
NO
NO
NO
NO
YES
YES
YES
YES
YES
YES
YES
YES
CHECK
C1 = 0x90
CHECK
CHECK
ENTER
BLPE MODE ?
C2 = 0x1E
(C2[LP] = 1)
CHECK
CHECK
C1 = 0x10
CHECK
CONTINUE
IN PEE MODE
S[PLLST] = 1?
S[LOCK] = 1?
S[CLKST] = %10?
S[CLKST] = %11?
(S[LP]=1)
S[IREFST] = 0?
S[OSCINIT] = 1?
C5 = 0x01
(C5[VDIV] = 1)
Figure 25-3. Flowchart of FEI to PEE mode transition using an 4 MHz crystal
Chapter 25 Multipurpose Clock Generator (MCG)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 571