NXP Semiconductors K22F series - Page 595

while a flash access is in progress can lead to non-deterministic
behavior.
Table 28-1. FMC register access
Registers Read access Write access
Mode Length Mode Length
Control registers:
PFAPR, PFB0CR,
PFB1CR
Supervisor (privileged)
mode or user mode
32 bits Supervisor (privileged)
mode only
32 bits
Cache registers Supervisor (privileged)
mode or user mode
32 bits Supervisor (privileged)
mode only
32 bits
NOTE
Accesses to unimplemented registers within the FMC's 4 KB
address space return a bus error.
The cache entries, both data and tag/valid, can be read at any time.
NOTE
System software is required to maintain memory coherence
when any segment of the flash cache is programmed. For
example, all buffer data associated with the reprogrammed flash
should be invalidated. Accordingly, cache program visible
writes must occur after a programming or erase event is
completed and before the new memory image is accessed.
The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and
the sets are numbered 0-7. The following table elaborates on the tag/valid and data
entries.
Table 28-2. Program visible cache registers
Cache
storage
Based at
offset
Contents of 32-bit read Nomenclature Nomenclature example
Tag 100h 13'h0, tag[18:5], 4'h0, valid In TAGVDWxSy, x denotes the way
and y denotes the set.
TAGVDW2S0 is the 14-bit tag
and 1-bit valid for cache entry
way 2, set 0.
Data 200h Upper or lower longword of
data
In DATAWxSyU and DATAWxSyL, x
denotes the way, y denotes the set,
and U and L represent upper and
lower word, respectively.
DATAW1S0U represents bits
[63:32] of data entry way 1,
set 0, and DATAW1S0L
represents bits [31:0] of data
entry way 1, set 0.
Chapter 28 Flash Memory Controller (FMC)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 595