NXP Semiconductors K22F series - Page 626

28.5.4.2.5 Access Check Evaluation
The flash controller FAC provides a cycle-by-cycle evaluation of the access rights for
each data transaction routed to the on-chip flash memory.
The entire flash storage capacity is partitioned into equal sized segments. Two registers
include a supervisor-only access control indicator and a execute-only access control
indicator for each segment.
The FAC logic performs the required access control evaluation using the reference
address and a 2-bit attribute (or "protection" field) as inputs from the bus cycle plus the
contents of the programming model registers.
The following code example illustrates C code for FAC evaluation:
unsigned long long sacc; // supervisor-only map
unsigned long long xacc; // execute-only map
unsigned int seg_size; // 8-bit segment size
unsigned int fac_error;
fac_evaluation (addr, prot)
unsigned int addr; // access address
unsigned int hprot; // encoded 2-bit "protection" field {supv, data}
{
unsigned int sacc_flag; // sacc flag for this segment
unsigned int xacc_flag; // xacc flag for this segment
unsigned int i; // segment index
i = (addr >> (8 + seg_size & 0x0f)) & 0x3f; // form 6-bit segment index
sacc_flag = (sacc >> i) & 1; // extract sacc bit for this segment
xacc_flag = (xacc >> i) & 1; // extract xacc bit for this segment
// create a 4-tuple concatenating the 2-bit protection field + {sacc, xacc} flags
switch ((hprot & 3) << 2 | (sacc_flag << 1) | xacc_flag) {
// all these combinations are allowed accesses
case 0x2: // {user, ifetch} && {supv+user, ifetch-only}
case 0x3: // {user, ifetch} && {supv+user, ifetch+data}
case 0x7: // {user, data} && {supv+user, ifetch+data}
case 0x8: // {supv, ifetch} && {supv-only, ifetch-only}
case 0x9: // {supv, ifetch} && {supv-only, ifetch+data}
case 0xa: // {supv, ifetch} && {supv+user, ifetch-only}
case 0xb: // {supv, ifetch} && {supv+user, ifetch+data}
case 0xd: // {supv, data} && {supv-only, ifetch+data}
case 0xf: // {supv, data} && {supv+user, ifetch+data}
fac_error = 00;
break;
// all these combinations are unallowed, that is, errored accesses
case 0x0: // {user, ifetch} && {supv-only, ifetch-only}
case 0x1: // {user, ifetch} && {supv-only, ifetch+data}
case 0x4: // {user, data} && {supv-only, ifetch-only}
case 0x5: // {user, data} && {supv-only, ifetch+data}
case 0x6: // {user, data} && {supv+user, ifetch-only}
case 0xc: // {supv, data} && {supv-only, ifetch-only}
case 0xe: // {supv, data} && {supv+user, ifetch-only}
fac_error = 1;
break;
} // switch()
} // fac_evaluation()
Functional description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
626 NXP Semiconductors