Address
Address
TSIZ=01
AA=1
AA=0
AA=1
AA=0
FB_CLK
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB_TSIZ[1:0]
S0 S1 S2 S3 S0
TIP
Single Byte-Write Transfer
Write8b.svg
FB_AD[23:0 ]
FB_AD[31:24 ]
Data[7:0]
Figure 31-8. Single Byte-Write Transfer
31.4.11.3.2
Bus Cycle Sizing—Word Transfer, 16-bit Device, No Wait
States
The following figure illustrates the basic word read transfer to a 16-bit device with no
wait states.
• The address is driven on the full FB_AD[31:8] bus in the first clock.
• The device tristates FB_AD[31:16] on the second clock and continues to drive
address on FB_AD[15:0] throughout the bus cycle.
• The external device returns the read data on FB_AD[31:16] and may tristate the data
line or continue driving the data one clock after FB_TA is sampled asserted.
Chapter 31 External Bus Interface (FlexBus)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 715
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