Address
Address
TSIZ=00
AA=1
AA=0
AA=1
AA=0
FB_CLK
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB_TSIZ[1:0]
S0 S1 S2 S3 S0
TIP
S0 S1 S2 S3 S0
Longword-Write Transfer
Write32b.svg
FB_AD[23:0 ]
FB_AD[31:0 ]
Data[31:0]
Figure 31-12. Longword-Write Transfer
31.4.11.4
Timing Variations
The FlexBus module has several features that can change the timing characteristics of a
basic read- or write-bus cycle to provide additional address setup, address hold, and time
for a device to provide or latch data.
31.4.11.4.1
Wait States
Wait states can be inserted before each beat of a transfer by programming the CSCRn
registers. Wait states can give the peripheral or memory more time to return read data or
sample write data.
The following figures show the basic read and write bus cycles (also shown in Figure
31-4 and Figure 31-9) with the default of no wait states respectively.
Chapter 31 External Bus Interface (FlexBus)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 719
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