Address
Address Data
TSIZ
AA=1
AA=0
AA=1
AA=0
FB_CLK
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB_TSIZ[1:0]
Basic Write-Bus Cycle (No Wait States)
basicWrite.svg
FB_AD[31:X] indicates a 32-, 16-, 8-bit address/data bus (or custom size).
FB_AD[Y:0] indicates a 32-, 16-, 8-bit address bus (or custom size).
FB_AD[Y :0]
FB_AD[31:X ]
Figure 31-14. Basic Write-Bus Cycle (No Wait States)
If wait states are used, the S1 state repeats continuously until the chip-select auto-
acknowledge unit asserts internal transfer acknowledge or the external FB_TA is
recognized as asserted. The following figures show a read and write cycle with one wait
state respectively.
Chapter 31 External Bus Interface (FlexBus)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 721
To Next Page
Loading...
