Address
Address Data
TSIZ
AA=1
AA=0
AA=1
AA=0
FB_CLK
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB_TSIZ[1:0]
S0 AS S2 S3 S0S1
Address Setup
Write2AS.svg
S0 AS S2 S3 S0S1
Write-Bus Cycle with 2-Clock Address Setup (No Wait States)
TIP
FB_AD[
Y :0]
FB_AD[31:X ]
FB_AD[31:X] indicates a 32-, 16-, 8-bit address/data bus (or custom size).
FB_AD[Y:0] indicates a 32-, 16-, 8-bit address bus (or custom size).
Figure 31-18. Write-Bus Cycle with Two Clock Address Setup (No Wait States)
In addition to address setup, a programmable address hold option for each chip select
exists. Address and attributes can be held one to four clocks after chip-select, byte-
selects, and output-enable negate. The following figures show read and write bus cycles
with two clocks of address hold respectively.
Chapter 31 External Bus Interface (FlexBus)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 725
To Next Page
Loading...
