NXP Semiconductors K22F series - Page 763

SC1A
ADHWTSA
ADHWTSn
Compare true
ADCH
complete
ADTRG
ADCO
Control Registers
SC1n
ADIV
ADICLK
Async
Clock Gen
ADACKEN
2
ALTCLK
ADACK
ADCK
MODE
transfer
CV2
CV1:CV2
TempM
DADM3
DADM0
DADP3
DADP0
Interrupt
1
ADVINP
ADVINM
ACFE
1
SC2
Rn
RA
CFG1,2
CLMx
CLMx
Compare true
MCU STOP
ADHWT
AD4
AD23
TempP
V REFH
VALTH
VREFL
VALTL
AIEN
COCO
trigger
DIFF
MODE
CLPx
PG, MG
PG, MG
CLPx
Calibration
OFS
CALF
CAL
SC3
CV1
ACFGT, ACREN
D
AVGE, AVGS
ADCOFS
V
REFSH
V
REFSL
(SC2, CFG1, CFG2)
Conversion
trigger
control
Clock
divide
Control sequencer
Bus clock
SAR converter
Compare
logic
Offset subtractor
Averager
Formatting
ADLSMP/ADLSTS
ADLPC/ADHSC
initialize
sample
convert
transfer
abort
Chapter 34 Analog-to-Digital Converter (ADC)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 763