NXP Semiconductors K22F series

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K22F Sub-Family Reference Manual, Rev. 4, 08/2016

890 NXP Semiconductors

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Default Chapter3
- Table of Contents3
Chapter 1 About this Document47
- Overview47
  - Purpose47
  - Audience47
- Conventions47
Chapter 2 Introduction49
- Overview49
- Module Functional Categories49
- Orderable Part Numbers55
Chapter 3 Chip Configuration57
- Introduction57
- Core Modules57
- System Modules67
- Clock Modules81
- Memories and Memory Interfaces84
- Security95
  - CRC Configuration95
  - RNG Configuration96
- Analog97
- Timers108
- Communication Interfaces121
- Human-Machine Interfaces137
  - GPIO Configuration137
Chapter 4 Memory Map139
- Introduction139
- System Memory Map139
  - Aliased Bit-Band Regions141
  - Flash Access Control Introduction142
- Flash Memory Map142
  - Alternate Non-Volatile IRC User Trim Description143
- SRAM Memory Map143
- Peripheral Bridge (AIPS-Lite) Memory Map144
  - Read-After-Write Sequence and Required Serialization of Memory Operations144
  - Peripheral Bridge 0 (AIPS-Lite 0) Memory Map144
- Private Peripheral Bus (PPB) Memory Map148
Chapter 5 Clock Distribution151
- Introduction151
- Programming Model151
- High-Level Device Clocking Diagram151
- Clock Definitions152
  - Device Clock Summary153
- Internal Clocking Requirements156
  - Clock Divider Values after Reset157
  - VLPR Mode Clocking157
- Clock Gating158
- Module Clocks158
Chapter 6 Reset and Boot169
- Introduction169
- Reset170
- Boot177
Chapter 7 Power Management181
- Introduction181
- Clocking Modes181
- Power Modes Description185
- Entering and Exiting Power Modes187
- Power Mode Transitions188
- Power Modes Shutdown Sequencing189
- Flash Program Restrictions190
- Module Operation in Low Power Modes190
Chapter 8 Security195
- Introduction195
- Flash Security195
- Security Interactions with Other Modules196
Chapter 9 Debug199
- Introduction199
  - References201
- The Debug Port201
  - JTAG-To-SWD Change Sequence202
  - JTAG-To-Cjtag Change Sequence202
- Debug Port Pin Descriptions203
- System TAP Connection203
  - IR Codes204
- JTAG Status and Control Registers204
  - MDM-AP Control Register205
  - MDM-AP Status Register207
- Debug Resets208
- Ahb-Ap209
- Itm209
- Core Trace Connectivity210
- Tpiu210
- Dwt210
- Debug in Low Power Modes211
  - Debug Module State in Low Power Modes211
- Debug & Security212
Chapter 10 Signal Multiplexing and Signal Descriptions213
- Introduction213
- Signal Multiplexing Integration213
- Pinout215
  - K22F Signal Multiplexing and Pin Assignments215
  - K22 Pinouts222
- Module Signal Description Tables228
Chapter 11 Port Control and Interrupts (PORT)239
- Introduction239
- Overview239
  - Features239
  - Modes of Operation240
- External Signal Description241
- Detailed Signal Description241
- Memory Map and Register Definition241
- Functional Description254
Chapter 12 System Integration Module (SIM)259
- Introduction259
  - Features259
- Memory Map and Register Definition260
- Functional Description291
Chapter 13 Kinetis Flashloader293
- Chip-Specific Information293
- Introduction293
- Functional Description295
- Peripherals Supported327
- Get/Setproperty Command Properties336
  - Property Definitions338
- Kinetis Flashloader Status Error Codes339
Reset Control Module (RCM)341
- Introduction341
- Reset Memory Map and Register Descriptions341
Chapter 15 System Mode Controller (SMC)351
- Introduction351
- Modes of Operation351
- Memory Map and Register Descriptions353
- Functional Description359
Chapter 16 Power Management Controller (PMC)371
- Introduction371
- Features371
- Low-Voltage Detect (LVD) System371
- I/O Retention373
- Memory Map and Register Descriptions373
Chapter 17 Low-Leakage Wakeup Unit (LLWU)379
- Introduction379
- LLWU Signal Descriptions382
- Memory Map/Register Definition382
- Functional Description396
Chapter 18 Miscellaneous Control Module (MCM)399
- Introduction399
  - Features399
- Memory Map/Register Descriptions399
- Functional Description405
  - Interrupts405
Chapter 19 Crossbar Switch Lite (AXBS-Lite)407
- Introduction407
  - Features407
- Memory Map / Register Definition408
- Functional Description408
  - General Operation408
  - Arbitration409
- Initialization/Application Information410
Chapter 20 Peripheral Bridge (AIPS-Lite)411
- Introduction411
  - Features411
  - General Operation411
- Memory Map/Register Definition412
- Functional Description412
  - Access Support412
Chapter 21 Direct Memory Access Multiplexer (DMAMUX)413
- Introduction413
- External Signal Description415
- Memory Map/Register Definition415
  - Channel Configuration Register (Dmamux_Chcfgn)416
- Functional Description417
- Initialization/Application Information421
  - Reset421
  - Enabling and Configuring Sources421
Chapter 22 Enhanced Direct Memory Access (Edma)425
- Introduction425
  - Edma System Block Diagram425
  - Block Parts426
  - Features427
- Modes of Operation428
- Memory Map/Register Definition429
  - TCD Memory429
  - TCD Initialization429
  - TCD Structure430
  - Reserved Memory and Bit Fields430
- Control Register (DMA_CR)441
- Error Status Register (DMA_ES)444
- Enable Request Register (DMA_ERQ)446
- Enable Error Interrupt Register (DMA_EEI)448
- Clear Enable Error Interrupt Register (DMA_CEEI)450
- Set Enable Error Interrupt Register (DMA_SEEI)451
- Clear Enable Request Register (DMA_CERQ)452
- Set Enable Request Register (DMA_SERQ)453
- Clear DONE Status Bit Register (DMA_CDNE)454
- Set START Bit Register (DMA_SSRT)455
- Clear Error Register (DMA_CERR)456
- Clear Interrupt Request Register (DMA_CINT)457
- Interrupt Request Register (DMA_INT)458
- Error Register (DMA_ERR)460
- Hardware Request Status Register (DMA_HRS)463
- Enable Asynchronous Request in Stop Register (DMA_EARS)466
- Channel N Priority Register (Dma_Dchprin)468
- TCD Source Address (Dma_Tcdn_Saddr)469
- TCD Signed Source Address Offset (Dma_Tcdn_Soff)469
- TCD Transfer Attributes (Dma_Tcdn_Attr)470
- TCD Minor Byte Count (Minor Loop Mapping Disabled) (Dma_Tcdn_Nbytes_Mlno)471
- TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)472
  - (Dma_Tcdn_Nbytes_Mloffno)472
- TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)473
  - (Dma_Tcdn_Nbytes_Mloffyes)473
- TCD Last Source Address Adjustment (Dma_Tcdn_Slast)474
- TCD Destination Address (Dma_Tcdn_Daddr)475
- TCD Signed Destination Address Offset (Dma_Tcdn_Doff)475
- TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (Dma_Tcdn_Citer_Elinkyes)476
  - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (Dma_Tcdn_Citer_Elinkno)477
  - TCD Last Destination Address Adjustment/Scatter Gather Address (Dma_Tcdn_Dlastsga)478
  - TCD Control and Status (Dma_Tcdn_Csr)479
  - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (Dma_Tcdn_Biter_Elinkyes)481
  - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (Dma_Tcdn_Biter_Elinkno)482
- Functional Description483
  - Edma Basic Data Flow483
  - Fault Reporting and Handling486
  - Channel Preemption489
  - Performance489
- Initialization/Application Information493
  - Edma Initialization493
  - Programming Errors495
  - Arbitration Mode Considerations496
  - Performing DMA Transfers496
  - Monitoring Transfer Descriptor Status500
  - Channel Linking502
  - Dynamic Programming503
  - Lockstep507
Chapter 23 External Watchdog Monitor (EWM)509
- Introduction509
- EWM Signal Descriptions512
- Memory Map/Register Definition512
- Functional Description515
Chapter 24 Watchdog Timer (WDOG)519
- Introduction519
- Features519
- Functional Overview520
- Testing the Watchdog525
  - Quick Test526
  - Byte Test526
- Backup Reset Generator527
- Generated Resets and Interrupts528
- Memory Map and Register Definition528
- Watchdog Operation with 8-Bit Access535
  - General Guideline535
  - Refresh and Unlock Operations with 8-Bit Access536
- Restrictions on Watchdog Operation537
Chapter 25 Multipurpose Clock Generator (MCG)539
- Introduction539
  - Features539
  - Modes of Operation543
- External Signal Description543
- Memory Map/Register Definition543
- Functional Description557
- Initialization / Application Information564
Chapter 26 Oscillator (OSC)577
- Introduction577
- Features and Modes577
- Block Diagram578
- OSC Signal Descriptions578
- External Crystal / Resonator Connections579
- External Clock Connections580
- Memory Map/Register Definitions581
  - OSC Memory Map/Register Definition581
- Functional Description583
- Reset587
- Low Power Modes Operation588
- Interrupts588
Chapter 27 RTC Oscillator (OSC32K)589
- Introduction589
  - Features and Modes589
  - Block Diagram589
- RTC Signal Descriptions590
  - EXTAL32 - Oscillator Input590
  - XTAL32 - Oscillator Output590
- External Crystal Connections591
- Memory Map/Register Descriptions591
- Functional Description591
- Reset Overview592
- Interrupts592
Chapter 28 Flash Memory Controller (FMC)593
- Introduction593
  - Overview593
  - Features594
- Modes of Operation594
- External Signal Description594
- Memory Map and Register Descriptions594
- Functional Description614
- Initialization and Application Information627
Chapter 29 Flash Memory Module (FTFA)629
- Introduction629
- External Signal Description632
- Memory Map and Registers633
- Functional Description648
- Overview681
Chapter 30682
- Block Diagram682
- Features682
- Modes of Operation682
- External Signal Descriptions683
- Command Definition684
  - Command Descriptions685
- Flash Memory Map for Ezport Access692
Chapter 31 External Bus Interface (Flexbus)693
- Introduction693
  - Definition693
  - Features694
- Signal Descriptions694
- Memory Map/Register Definition696
- Functional Description703
- Initialization/Application Information739
  - Initializing a Chip-Select739
  - Reconfiguring a Chip-Select739
Chapter 32 Cyclic Redundancy Check (CRC)741
- Introduction741
- Memory Map and Register Descriptions742
- Functional Description745
Chapter 33 Random Number Generator Accelerator (RNGA)751
- Introduction751
  - Overview751
- Modes of Operation752
  - Entering Normal Mode752
  - Entering Sleep Mode752
- Memory Map and Register Definition753
- Functional Description758
  - Output (OR) Register758
  - Core Engine / Control Logic758
- Initialization/Application Information759
Chapter 34 Analog-To-Digital Converter (ADC)761
- Introduction761
  - Features761
  - Block Diagram762
- ADC Signal Descriptions764
- Memory Map and Register Definitions766
- Functional Description789
- Initialization Information807
  - ADC Module Initialization Example807
- Application Information809
  - External Pins and Routing809
  - Sources of Error811
- Introduction817
Chapter 35817
- CMP Features817
- 6-Bit DAC Key Features818
- ANMUX Key Features818
- CMP, DAC and ANMUX Diagram819
- CMP Block Diagram820
- Memory Map/Register Definitions822
- Functional Description828
- CMP Interrupts841
- DMA Support841
- CMP Asynchronous DMA Support842
- Digital-To-Analog Converter843
- DAC Functional Description843
  - Voltage Reference Source Select843
- DAC Resets844
- DAC Clocks844
- DAC Interrupts844
Chapter 36845
- Introduction845
- Features845
- Block Diagram845
- Memory Map/Register Definition846
- Functional Description853
- Introduction857
  - Overview858
  - Features858
Chapter 37 Voltage Reference (VREFV1)859
- Modes of Operation859
- VREF Signal Descriptions859
- Memory Map and Register Definition860
  - VREF Trim Register (VREF_TRM)860
  - VREF Status and Control Register (VREF_SC)861
- Functional Description862
- Initialization/Application Information865
- Introduction867
  - Features867
  - Implementation868
Chapter 38 Programmable Delay Block (PDB)869
- Back-To-Back Acknowledgment Connections869
- DAC External Trigger Input Connections869
- Block Diagram869
- Modes of Operation871
- PDB Signal Descriptions871
- Memory Map and Register Definition871
- Functional Description883
- Application Information888
  - Impact of Using the Prescaler and Multiplication Factor on Timing Resolution888
Chapter 39 Flextimer Module (FTM)891
- Introduction891
- FTM Signal Descriptions896
- Memory Map and Register Definition896
- Functional Description946
- Reset Overview1024
- FTM Interrupts1025
- Initialization Procedure1026
Chapter 40 Periodic Interrupt Timer (PIT)1029
- Introduction1029
  - Block Diagram1029
  - Features1030
- Signal Description1030
- Memory Map/Register Description1031
- Functional Description1035
- Initialization and Application Information1037
- Example Configuration for Chained Timers1038
Chapter 41 Low-Power Timer (LPTMR)1041
- Introduction1041
  - Features1041
  - Modes of Operation1041
- LPTMR Signal Descriptions1042
  - Detailed Signal Descriptions1042
- Memory Map and Register Definition1042
- Functional Description1047
- Introduction1051
Chapter 421051
- Features1051
- Modes of Operation1051
- RTC Signal Descriptions1052
- Register Definition1053
- Functional Description1064
- Introduction1069
- Functional Description1072
  - Data Structures1072
  - On-Chip Transceiver Required External Components1073
- Programmers Interface1075
- Memory Map/Register Definitions1082
- OTG and Host Mode Operation1110
- Host Mode Operation Examples1110
- On-The-Go Operation1113
  - OTG Dual Role a Device Operation1114
  - OTG Dual Role B Device Operation1115
- Device Mode IRC48 Operation1117
  - Modes of Operation1121
- USB Voltage Regulator Module Signal Descriptions1121
- Introduction1123
Chapter 451123
- Block Diagram1123
- Features1124
- Interface Configurations1126
- Modes of Operation1126
- Module Signal Descriptions1128
- Memory Map/Register Definition1130
- Functional Description1151
- Initialization/Application Information1174
Chapter 46 Inter-Integrated Circuit (I2C)1181
- Introduction1181
- I2C Signal Descriptions1183
- Memory Map/Register Definition1184
- Functional Description1196
- Initialization/Application Information1211
Chapter 47 Universal Asynchronous Receiver/Transmitter (UART)1215
- Introduction1215
  - Features1215
  - Modes of Operation1217
- UART Signal Descriptions1218
  - Detailed Signal Descriptions1218
- Memory Map and Registers1219
  - UART Baud Rate Registers: High (Uartx_Bdh)1224
  - UART Baud Rate Registers: Low (Uartx_Bdl)1225
  - UART Control Register 1 (Uartx_C1)1226
- UART Control Register 2 (Uartx_C2)1227
- UART Status Register 1 (Uartx_S1)1229
- UART Status Register 2 (Uartx_S2)1232
- UART Control Register 3 (Uartx_C3)1234
- UART Data Register (Uartx_D)1235
- UART Match Address Registers 1 (Uartx_Ma1)1236
- UART Match Address Registers 2 (Uartx_Ma2)1237
- UART Control Register 4 (Uartx_C4)1237
- UART Control Register 5 (Uartx_C5)1238
- UART Extended Data Register (Uartx_Ed)1239
- UART Modem Register (Uartx_Modem)1240
- UART Infrared Register (Uartx_Ir)1241
- UART FIFO Parameters (Uartx_Pfifo)1242
- UART FIFO Control Register (Uartx_Cfifo)1243
- UART FIFO Status Register (Uartx_Sfifo)1244
- UART FIFO Transmit Watermark (Uartx_Twfifo)1245
- UART FIFO Transmit Count (Uartx_Tcfifo)1246
- UART FIFO Receive Watermark (Uartx_Rwfifo)1246
- UART FIFO Receive Count (Uartx_Rcfifo)1247
- UART 7816 Control Register (Uartx_C7816)1247
- UART 7816 Interrupt Enable Register (Uartx_Ie7816)1249
- UART 7816 Interrupt Status Register (Uartx_Is7816)1250
- UART 7816 Wait Parameter Register (Uartx_Wp7816)1252
- UART 7816 Wait N Register (Uartx_Wn7816)1252
- UART 7816 Wait FD Register (Uartx_Wf7816)1253
- UART 7816 Error Threshold Register (Uartx_Et7816)1253
- UART 7816 Transmit Length Register (Uartx_Tl7816)1254
- UART 7816 ATR Duration Timer Register a (Uartx_Ap7816A_T0)1254
- UART 7816 ATR Duration Timer Register B (Uartx_Ap7816B_T0)1255
  - UART 7816 Wait Parameter Register a (Uartx_Wp7816A_T0)1256
  - UART 7816 Wait Parameter Register a (Uartx_Wp7816A_T1)1256
  - UART 7816 Wait Parameter Register B (Uartx_Wp7816B_T0)1257
  - UART 7816 Wait Parameter Register B (Uartx_Wp7816B_T1)1257
  - UART 7816 Wait and Guard Parameter Register (Uartx_Wgp7816_T1)1258
  - UART 7816 Wait Parameter Register C (Uartx_Wp7816C_T1)1258
- Functional Description1259
  - Transmitter1259
  - Receiver1265
  - Baud Rate Generation1279
  - Data Format (Non ISO-7816)1281
  - Single-Wire Operation1284
  - Loop Operation1285
  - ISO-7816/Smartcard Support1285
  - Infrared Interface1291
- Reset1292
- System Level Interrupt Sources1292
  - RXEDGIF Description1292
- DMA Operation1293
- Application Information1294
  - Transmit/Receive Data Buffer Operation1294
  - Initialization Sequence1294
  - Initialization Sequence (Non ISO-7816)1296
  - Overrun (OR) Flag Implications1297
  - Overrun NACK Considerations1298
  - Match Address Registers1299
  - Modem Feature1299
  - Irda Minimum Pulse Width1300
  - Clearing 7816 Wait Timer (WT, BWT, CWT) Interrupts1300
  - Legacy and Reverse Compatibility Considerations1301
Chapter 48 Low Power Universal Asynchronous Receiver/Transmitter (LPUART)1303
- Introduction1303
- Register Definition1306
- Functional Description1322
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)1337
- Introduction1337
- External Signals1339
- Memory Map and Register Definition1340
- Functional Description1364
- Introduction1375
  - Features1375
  - Modes of Operation1375
Chapter 50 General-Purpose Input/Output (GPIO)1376
- GPIO Signal Descriptions1376
- Memory Map and Register Definition1377
- Functional Description1382
  - General-Purpose Input1382
  - General-Purpose Output1382
Chapter 51 JTAG Controller (JTAGC)1383
- Introduction1383
- External Signal Description1386
- Register Description1387
- Functional Description1389
- Initialization/Application Information1394

NXP Semiconductors K22F series - Page 890

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