CAPTEST
no clock selected
(FTM counter disable)
system clock
fixed frequency clock
external clock
phase A
phase B
CLKS
FTMEN
QUADEN
synchronizer
Quadrature
decoder
QUADEN
CPWMS
PS
INITTRIGEN
TOIE
TOF
TOFDIR
QUADIR
CNTIN
MOD
FAULTIN
FAULTF
FAULTFn*
FTM counter
FAULTM[1:0]
FFVAL[3:0]
FAULTIE
FAULTnEN*
FFLTRnEN*
fault input n*
fault control
*where n = 3, 2, 1, 0
initialization
trigger
timer overflow
interrupt
fault condition
fault interrupt
pair channels 0 - channels 0 and 1
DECAPEN
COMBINE0
CPWMS
MS0B:MS0A
ELS0B:ELS0A
dual edge capture
mode logic
input capture
mode logic
input capture
mode logic
channel 0
input
channel 1
input
DECAPEN
COMBINE0
CPWMS
MS1B:MS1A
ELS1B:ELS1A
DECAPEN
COMBINE3
CPWMS
MS6B:MS6A
ELS6B:ELS6A
channel 6
input
channel 7
input
DECAPEN
COMBINE3
CPWMS
MS7B:MS7A
ELS7B:ELS7A
dual edge capture
mode logic
input capture
mode logic
input capture
mode logic
C0V
C1V
C6V
C7V
CH6IE
CH6F
CH1IE
CH0IE
CH7IE
CH7F
CH1F
CH0F
channel 0
interrupt
channel 1
interrupt
channel 6
interrupt
channel 7
interrupt
channel 7
match trigger
channel 6
output signal
channel 6
match trigger
channel 1
match trigger
channel 0
output signal
channel 0
match trigger
channel 1
output signal
channel 7
output signal
CH7TRIG
CH6TRIG
CH1TRIG
CH0TRIG
pair channels 3 - channels 6 and 7
(generation of channels 0 and 1 outputs signals in output
compare, EPWM, CPWM and combine modes according to
initialization, complementary mode, inverting, software output
control, deadtime insertion, output mask, fault control
and polarity control)
output modes logic
(generation of channels 6 and 7 outputs signals in output
compare, EPWM, CPWM and combine modes according to
initialization, complementary mode, inverting, software output
control, deadtime insertion, output mask, fault control
and polarity control)
output modes logic
prescaler
(1, 2, 4, 8, 16, 32, 64 or 128)
Figure 39-1. FTM block diagram
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
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