NXP Semiconductors K22F series - Page 964

If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced low at the beginning of
the period (FTM counter = CNTIN) and at the channel (n+1) match (FTM counter = C(n
+1)V). It is forced high at the channel (n) match (FTM counter = C(n)V). See the
following figure.
If (ELSnB:ELSnA = X:1), then the channel (n) output is forced high at the beginning of
the period (FTM counter = CNTIN) and at the channel (n+1) match (FTM counter = C(n
+1)V). It is forced low at the channel (n) match (FTM counter = C(n)V). See the
following figure.
In Combine mode, the ELS(n+1)B and ELS(n+1)A bits are not used in the generation of
the channels (n) and (n+1) output. However, if (ELSnB:ELSnA = 0:0) then the channel
(n) output is not controlled by FTM, and if (ELS(n+1)B:ELS(n+1)A = 0:0) then the
channel (n+1) output is not controlled by FTM.
FTM counter
channel (n) match
channel (n) output
with ELSnB:ELSnA = X:1
with ELSnB:ELSnA = 1:0
channel (n) output
channel (n+1) match
Figure 39-25. Combine mode
The following figures illustrate the PWM signals generation using Combine mode.
FTM counter
channel (n) output
with ELSnB:ELSnA = 1:0
channel (n) output
with ELSnB:ELSnA = X:1
MOD
C(n)V
CNTIN
C(n+1)V
Figure 39-26. Channel (n) output if (CNTIN < C(n)V < MOD) and (CNTIN < C(n+1)V < MOD)
and (C(n)V < C(n+1)V)
Functional description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
964 NXP Semiconductors