DocID024597 Rev 3 211/1693
RM0351 Reset and clock control (RCC)
253
6.4.7 Clock interrupt enable register (RCC_CIER)
Address offset: 0x18
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8765432 1 0
Res. Res. Res. Res. Res. Res.
LSE
CSSIE
Res.
PLL
SAI2
RDYIE
PLL
SAI1
RDYIE
PLL
RDYIE
HSE
RDYIE
HSI
RDYIE
MSI
RDYIE
LSE
RDYIE
LSI
RDYIE
rw rw rw rw rw rw rw rw rw
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 LSECSSIE: LSE clock security system interrupt enable
Set and cleared by software to enable/disable interrupt caused by the clock security system
on LSE.
0: Clock security interrupt caused by LSE clock failure disabled
1: Clock security interrupt caused by LSE clock failure enabled
Bit 8 Reserved, must be kept at reset value.
Bit 7 PLLSAI2RDYIE: PLLSAI2 ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLLSAI2 lock.
0: PLLSAI2 lock interrupt disabled
1: PLLSAI2 lock interrupt enabled
Bit 6 PLLSAI1RDYIE: PLLSAI1 ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLSAI1L lock.
0: PLLSAI1 lock interrupt disabled
1: PLLSAI1 lock interrupt enabled
Bit 5 PLLRDYIE: PLL ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
Bit 4 HSERDYIE: HSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSE oscillator
stabilization.
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
Bit 3 HSIRDYIE: HSI16 ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator
stabilization.
0: HSI16 ready interrupt disabled
1: HSI16 ready interrupt enabled
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