Flexible static memory controller (FSMC) RM0351
370/1693 DocID024597 Rev 3
1. The memory asserts the WAIT signal aligned to NOE/NWE which toggles:
2. The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):
if
then:
otherwise
where max_wait_assertion_time is the maximum time taken by the memory to assert
the WAIT signal once NEx/NOE/NWE is low.
Figure 44 and Figure 45 show the number of HCLK clock cycles that are added to the
memory access phase after WAIT is released by the asynchronous memory (independently
of the above cases).
Figure 44. Asynchronous wait during a read access waveforms
1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register.
DATAST 4 HCLK×()max_wait_assertion_time+≥
max_wait_assertion_time address_phase hold_phase+>
DATAST 4 HCLK×()max_wait_assertion_time address_phase– hold_phase–()+≥
$>@
12(
+&/.
0HPRU\WUDQVDFWLRQ
'>@
1([
GDWDGULYHQE\PHPRU\
069
DGGUHVVSKDVH
GDWDVHWXSSKDVH
.7!)4
DONTCARE DONTCARE
To Next Page
Loading...
Need help?
General
