Power control (PWR) RM0351
138/1693 DocID024597 Rev 3
contents of the registers and internal SRAM1 and SRAM2.
• In Stop 1 and Stop 2 modes, the main regulator is off and the low-power regulator
(LPR) supplies low power to the V
CORE
domain, preserving the contents of the
registers and of internal SRAM1 and SRAM2.
• In Standby mode with SRAM2 content preserved (RRS bit is set in the PWR_CR3
register), the main regulator (MR) is off and the low-power regulator (LPR) provides the
supply to SRAM2 only. The core and digital peripherals (except Standby circuitry and
backup domain) and SRAM1 are powered off.
• In Standby mode, both regulators are powered off. The contents of the registers and of
SRAM1 and SRAM2 is lost except for the Standby circuitry and the backup domain.
• In Shutdown mode, both regulators are powered off. When exiting from Shutdown
mode, a power-on reset is generated. Consequently, the contents of the registers and
SRAM1 and SRAM2 is lost, except for the backup domain.
5.1.7 Dynamic voltage scaling management
The dynamic voltage scaling is a power management technique which consists in
increasing or decreasing the voltage used for the digital peripherals (V
CORE
), according to
the application performance and power consumption needs.
Dynamic voltage scaling to increase V
CORE
is known as overvolting. It allows to improve the
device performance.
Dynamic voltage scaling to decrease V
CORE
is known as undervolting. It is performed to
save power, particularly in laptop and other mobile devices where the energy comes from a
battery and is thus limited.
• Range 1: High-performance range.
The main regulator provides a typical output voltage at 1.2 V. The system clock frequency
can be up to 80 MHz. The Flash access time for read access is minimum, write and erase
operations are possible.
• Range 2: Low-power range.
The main regulator provides a typical output voltage at 1.0 V. The system clock frequency
can be up to 26 MHz.The Flash access time for a read access is increased as compared to
Range 1; write and erase operations are possible.
Voltage scaling is selected through the VOS bit in the PWR_CR1 register.
The sequence to go from Range 1 to Range 2 is:
1. Reduce the system frequency to a value lower than 26 MHz.
2. Adjust number of wait states according new frequency target in Range2 (LATENCY bits
in the FLASH_ACR).
3. Program the VOS bits to “10” in the PWR_CR1 register.
The sequence to go from Range 2 to Range 1 is:
1. Program the VOS bits to “01” in the PWR_CR1 register.
2. Wait until the VOSF flag is cleared in the PWR_SR2 register.
3. Adjust number of wait states according new frequency target in Range1 (LATENCY bits
in the FLASH_ACR).
4. Increase the system frequency.
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