SD/SDIO/MMC card host interface (SDMMC) RM0351
1442/1693 DocID024597 Rev 3
41.8.10 SDMMC data counter register (SDMMC_DCOUNT)
Address offset: 0x30
Reset value: 0x0000 0000
The SDMMC_DCOUNT register loads the value from the data length register (see
SDMMC_DLEN) when the DPSM moves from the Idle state to the Wait_R or Wait_S state.
As data is transferred, the counter decrements the value until it reaches 0. The DPSM then
moves to the Idle state and the data status end flag, DATAEND, is set.
Note: This register should be read only when the data transfer is complete.
41.8.11 SDMMC status register (SDMMC_STA)
Address offset: 0x34
Reset value: 0x0000 0000
The SDMMC_STA register is a read-only register. It contains two types of flag:
• Static flags (bits [23:22,10:0]): these bits remain asserted until they are cleared by
writing to the SDMMC Interrupt Clear register (see SDMMC_ICR)
• Dynamic flags (bits [21:11]): these bits change state depending on the state of the
underlying logic (for example, FIFO full and empty flags are asserted and deasserted
as data while written to the FIFO)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. DATACOUNT[24:16]
rrrrrrrrr
1514131211109876543210
DATACOUNT[15:0]
rrrrrrrrrrrrrrrr
Bits 31:25 Reserved, must be kept at reset value.
Bits 24:0 DATACOUNT: Data count value
When this bit is read, the number of remaining data bytes to be transferred is returned. Write
has no effect.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. SDIOIT
RXD
AVL
TXD
AVL
RX
FIFOE
TX
FIFOE
RX
FIFOF
TX
FIFOF
r r rrrrr
1514131211109876 5 43210
RX
FIFO
HF
TX
FIFO
HE
RXACT TXACT
CMD
ACT
DBCK
END
Res.
DATA
END
CMDS
ENT
CMDR
END
RX
OVERR
TXUND
ERR
DTIME
OUT
CTIME
OUT
DCRC
FAIL
CCRC
FAIL
rrrrrr rrr r rrrrr
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 SDIOIT: SDIO interrupt received
Bit 21 RXDAVL: Data available in receive FIFO
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