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ST STM32L4x6 User Manual

ST STM32L4x6
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Single Wire Protocol Master Interface (SWPMI) RM0351
1382/1685 DocID024597 Rev 3
Bit 2 RXMODE: Reception buffering mode
This bit is used to choose the reception buffering mode. This bit is relevant only when
TXDMA bit is set (refer to Table 217: Buffer modes selection for transmission/reception).
0: SWPMI is configured in Single software buffer mode for reception
1: SWPMI is configured in Multi software buffer mode for reception.
Note: This bit cannot be written while SWPACT bit is set.
Bit 1 TXDMA: Transmission DMA enable
This bit is used to enable the DMA mode in transmission
0: DMA is disabled for transmission
1: DMA is enabled for transmission
Note: TXDMA is automatically cleared if the payload size of the transmitted frame is given as
0x00 (in the least significant byte of TDR for the first word of a frame). TXDMA is also
automatically cleared on underrun events (when TXUNRF flag is set in the SWP_ISR
register)
Bit 0 RXDMA: Reception DMA enable
This bit is used to enable the DMA mode in reception
0: DMA is disabled for reception
1: DMA is enabled for reception
Table 217. Buffer modes selection for transmission/reception
Buffer mode No software buffer Single software buffer Multi software buffer
RXMODE/TXMODE x 0 1
RXDMA/TXDMA 0 1 1

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ST STM32L4x6 Specifications

General IconGeneral
BrandST
ModelSTM32L4x6
CategoryMicrocontrollers
LanguageEnglish

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