Advanced encryption standard hardware accelerator (AES) RM0351
732/1693 DocID024597 Rev 3
Figure 182. Mode 1: encryption with 128-bit key length
25.9.2 Mode 2: key derivation
1. Disable the AES by resetting the EN bit in the AES_CR register.
2. Configure mode 2 by programming MODE[1:0] = 01 in the AES_CR register.
Note: CHMOD[2:0] bits are not significant in this case because this key derivation mode is
independent from the chaining algorithm selected.
3. Select key length 128-bit or 256-bit via KEYSIZE bits configuration in AES_CR register.
4. Write the AES_KEYRx registers with the encryption key to obtain the derivative key. A
write to the AES_IVRx has no effect.
5. Enable the AES by setting the EN bit in the AES_CR register.
6. Wait until the CCF flag is set in the AES_SR register.
7. The derivation key is put automatically into the AES_KEYRx registers. Read the
AES_KEYRx registers to obtain the decryption key if needed. The AES is disabled by
hardware. To restart a derivation key calculation, repeat steps 3, 4, 5 and 6.
Figure 183. Mode 2: key derivation with 128-bit key length
069
:5
37
:5
37
:5
37
:5
37
:DLWXQWLOIODJ&&)
5'
&7
5'
&7
5'
&7
5'
&7
,QSXWSKDVH
ZULWHRSHUDWLRQVLQWR
$(6B',1>@
&RPSXWDWLRQSKDVH
2XWSXWSKDVH
UHDGRSHUDWLRQVRI
$(6B'287>@
37 SODLQWH[W ZRUGV37«37
&7 F\SKHUWH[W ZRUGV&7«&7
06% /6% 06% /6%
069
:5
(.
:5
(.
:5
(.
:5
(.
:DLWXQWLOIODJ&&)
5'
'.
5'
'.
5'
'.
5'
'.
,QSXWSKDVH
ZULWHRSHUDWLRQVLQWR
$(6B.(<5[>@
&RPSXWDWLRQSKDVH
2XWSXWSKDVHRSWLRQDO
UHDGRSHUDWLRQVRI
$(6B.(<5[>@
(. HQFU\SWLRQNH\ ZRUGV(.«(.
'. GHFU\SWLRQNH\ ZRUGV'.«'.
06% /6% 06% /6%
(1 LQWR$(6B&5
ELWGHULYDWLRQNH\
VWRUHGLQWR$(6B.(<5[