Digital filter for sigma delta modulators (DFSDM) RM0351
640/1693 DocID024597 Rev 3
Note: For each of the flag bits, an interrupt can be enabled by setting the corresponding bit in
DFSDMx_CR2. If an interrupt is called, the flag must be cleared before exiting the interrupt
service routine.
All the bits of DFSDMx_ISR are automatically reset when DFEN=0.
21.7.4 DFSDM interrupt flag clear register (DFSDMx_ICR)
Address offset: 0x100 * (x+1) + 0x00C, x = 0...3
Reset value: 0x0000 0000
Bit 2 JOVRF: Injected conversion overrun flag
0: No injected conversion overrun has occurred
1: An injected conversion overrun has occurred, which means that an injected conversion finished
while JEOCF was already ‘1’. JDATAR is not affected by overruns
This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the
DFSDMx_ICR register.
Bit 1 REOCF: End of regular conversion flag
0: No regular conversion has completed
1: A regular conversion has completed and its data may be read
This bit is set by hardware. It is cleared when the software or DMA reads DFSDMx_RDATAR.
Bit 0 JEOCF: End of injected conversion flag
0: No injected conversion has completed
1: An injected conversion has completed and its data may be read
This bit is set by hardware. It is cleared when the software or DMA reads DFSDMx_JDATAR.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF[7:0] CLRCKABF[7:0]
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
CLRR
OVRF
CLR J
OVRF
Res. Res.
rc_w1 rc_w1
Bits 31:24 CLRSCDF[7:0]: Clear the short-circuit detector flag
CLRSCDF[y]=0: Writing ‘0’ has no effect
CLRSCDF[y]=1: Writing ‘1’ to position y clears the corresponding SCDF[y] bit in the DFSDMx_ISR
register
Note: CLRSCDF[7:0] is present only in DFSDM0_ICR register (filter x=0)
Bits 23:16 CLRCKABF[7:0]: Clear the clock absence flag
CLRCKABF[y]=0: Writing ‘0’ has no effect
CLRCKABF[y]=1: Writing ‘1’ to position y clears the corresponding CKABF[y] bit in the
DFSDMx_ISR register. When the transceiver is not yet synchronized, the clock absence flag is set
and cannot be cleared by CLRCKABF[y].
Note: CLRCKABF[7:0] is present only in DFSDM0_ICR register (filter x=0)
Bits 15:4 Reserved, must be kept at reset value.
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