SD/SDIO/MMC card host interface (SDMMC) RM0351
1408/1693 DocID024597 Rev 3
41.3.2 SDMMC APB2 interface
The APB2 interface generates the interrupt and DMA requests, and accesses the SDMMC
adapter registers and the data FIFO. It consists of a data path, register decoder, and
interrupt/DMA logic.
SDMMC interrupts
The interrupt logic generates an interrupt request signal that is asserted when at least one
of the selected status flags is high. A mask register is provided to allow selection of the
conditions that will generate an interrupt. A status flag generates the interrupt request if a
corresponding mask flag is set.
SDMMC/DMA interface
SDMMC APB interface controls all subunit to perform transfers between the host and card
Example of read procedure using DMA
Send CMD17 (READ_BLOCK) as follows:
a) Program the SDMMC data length register (SDMMC data timer register should be
already programmed before the card identification process)
b) Program DMA channel (please refer to DMA configuration for SDMMC controller)
c) Program the SDMMC data control register: DTEN with ‘1’ (SDMMC card host
enabled to send data); DTDIR with ‘1’ (from card to controller); DTMODE with ‘0’
(block data transfer); DMAEN with ‘1’ (DMA enabled); DBLOCKSIZE with 0x9
(512 bytes). Other fields are don’t care.
d) Program the SDMMC argument register with the address location of the card from
where data is to be transferred
e) Program the SDMMC command register: CmdIndex with 17(READ_BLOCK);
WaitResp with ‘1’ (SDMMC card host waits for a response); CPSMEN with ‘1’
(SDMMC card host enabled to send a command). Other fields are at their reset
value.
f) Wait for SDMMC_STA[6] = CMDREND interrupt, (CMDREND is set if there is no
error on command path).
g) Wait for SDMMC_STA[10] = DBCKEND, (DBCKEND is set in case of no errors
until the CRC check is passed)
h) Wait until the FIFO is empty, when FIFO is empty the SDMMC_STA[5] =
RXOVERR value has to be check to guarantee that read succeeded
Note: When FIFO overrun error occurs with last 1-4 bytes, it may happens that RXOVERR flag is
set 2 APB clock cycles after DATAEND flag is set. To guarantee success of read operation
RXOVERR must be cheked after FIFO is empty.
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