RM0351
74/1693 DocID024597 Rev 3
The write protection can be enabled in SYSCFG SRAM2 write protection register
(SYSCFG_SWPR) in the SYSCFG block. This is a register with write ‘1’ once mechanism,
which means by writing ‘1’ on a bit it will setup the write protection for that page of SRAM
and it can be removed/cleared by a system reset only.
2.4.3 SRAM2 Read protection
The SRAM2 is protected with the Read protection (RDP). Refer to Section 3.5.1: Read
protection (RDP) for more details.
2.4.4 SRAM2 Erase
The SRAM2 can be erased with a system reset using the option bit SRAM2_RST in the user
option byte (refer to Section 3.4.1: Option bytes description).
The SRAM2 erase can also be requested by software by setting the bit SRAM2ER in the
SYSCFG SRAM2 control and status register (SYSCFG_SCSR).
2.5 Flash memory overview
The Flash memory is composed of two distinct physical areas:
• The main Flash memory block. It contains the application program and user data if
necessary.
• The information block. It is composed of three parts:
– Option bytes for hardware and memory protection user configuration.
– System memory which contains the proprietary boot loader code.
– OTP (one-time programmable) area
The Flash interface implements instruction access and data access based on the AHB
protocol. It implements a system of instruction prefetch and caches lines that speeds up
Page 20 0x1000 5000 0x1000 53FF
Page 21 0x1000 5400 0x1000 57FF
Page 22 0x1000 5800 0x1000 5BFF
Page 23 0x1000 5C00 0x1000 5FFF
Page 24 0x1000 6000 0x1000 63FF
Page 25 0x1000 6400 0x1000 67FF
Page 26 0x1000 6800 0x1000 6BFF
Page 27 0x1000 6C00 0x1000 6FFF
Page 28 0x1000 7000 0x1000 73FF
Page 29 0x1000 7400 0x1000 77FF
Page 30 0x1000 7800 0x1000 7BFF
Page 31 0x1000 7C00 0x1000 7FFF
Table 2. SRAM2 organization (continued)
Page number Start address End address
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