DocID024597 Rev 3 463/1693
RM0351 Analog-to-digital converters (ADC)
540
Figure 86. Single conversions of a sequence, hardware trigger
1. TRGx (over-frequency) is selected as trigger source, EXTEN = 01, CONT = 0
2. Channels selected = 1, 2, 3, 4; AUTDLY=0.
Figure 87. Continuous conversions of a sequence, hardware trigger
1. TRGx is selected as trigger source, EXTEN = 10, CONT = 1
2. Channels selected = 1, 2, 3, 4; AUTDLY=0.
16.3.26 Data management
Data register, data alignment and offset (ADCx_DR, OFFSETy, OFFSETy_CH,
ALIGN)
Data and alignment
At the end of each regular conversion channel (when EOC event occurs), the result of the
converted data is stored into the ADCx_DR data register which is 16 bits wide.
At the end of each injected conversion channel (when JEOC event occurs), the result of the
converted data is stored into the corresponding ADCx_JDRy data register which is 16 bits
wide.
The ALIGN bit in the ADCx_CFGR register selects the alignment of the data stored after
conversion. Data can be right- or left-aligned as shown in Figure 88, Figure 89, Figure 90
and Figure 91.
069
(2&
(26
75*;
$'&B'5
5'<
&+ &+
5($'<
&+ &+ &+ &+ &+ &+ 5'<
' ' ' ' ''
E\VZ E\KZ
' '
WULJJHUHG LJQRUHG
$'67$57
$'&VWDWH
,QGLFDWLYHWLPLQJV
069
(2&
(26
75*[
$'&B'5
5'< &+ &+
&+
&+ &+ &+ &+ &+ &+
5'<
' ' ' ' ''
E\VZ E\KZ
1RWLQVFDOHWLPLQJV
' '
WULJJHUHG LJQRUHG
6723
$'673
$'67$57
$'&
To Next Page
Loading...
Need help?
General
