General-purpose timers (TIM15/16/17) RM0351
968/1693 DocID024597 Rev 3
28.5.3 TIM15 slave mode control register (TIM15_SMCR)
Address offset: 0x08
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SMS[3]
rw
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. MSM TS[2:0] Res. SMS[2:0]
rw rw rw rw rw rw rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 SMS[3]: Slave mode selection - bit 3
Refer to SMS description - bits 2:0
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 MSM: Master/slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful if we
want to synchronize several timers on a single external event.
Bits 6:4 TS[2:0]: Trigger selection
This bit field selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0)
001: Internal Trigger 1 (ITR1)
010: Internal Trigger 2 (ITR2)
011: Internal Trigger 3 (ITR3)
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
See Table 156: TIMx Internal trigger connection on page 969 for more details on ITRx
meaning for each Timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to
avoid wrong edge detections at the transition.
Bit 3 Reserved, must be kept at reset value.
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