ST STM32L4x6

Analog-to-digital converters (ADC) RM0351
432/1693 DocID024597 Rev 3
Clock ratio constraint between ADC clock and AHB clock
There are generally no constraints to be respected for the ratio between the ADC clock and
the AHB clock except if some injected channels are programmed. In this case, it is
mandatory to respect the following ratio:
• F
HCLK
>= F
ADC
/ 4 if the resolution of all channels are 12-bit or 10-bit
• F
HCLK
>= F
ADC
/ 3 if there are some channels with resolutions equal to 8-bit (and none
with lower resolutions)
• F
HCLK
>= F
ADC
/ 2 if there are some channels with resolutions equal to 6-bit
Figure 59. ADC clock scheme
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