Controller area network (bxCAN) RM0351
1470/1693 DocID024597 Rev 3
• The FIFO 1 interrupt can be generated by the following events:
– Reception of a new message, FMP1 bits in the CAN_RF1R register are not ‘00’.
– FIFO1 full condition, FULL1 bit in the CAN_RF1R register set.
– FIFO1 overrun condition, FOVR1 bit in the CAN_RF1R register set.
• The error and status change interrupt can be generated by the following events:
– Error condition, for more details on error conditions please refer to the CAN Error
Status register (CAN_ESR).
– Wakeup condition, SOF monitored on the CAN Rx signal.
– Entry into Sleep mode.
42.9 CAN registers
The peripheral registers have to be accessed by words (32 bits).
42.9.1 Register access protection
Erroneous access to certain configuration registers can cause the hardware to temporarily
disturb the whole CAN network. Therefore the CAN_BTR register can be modified by
software only while the CAN hardware is in initialization mode.
Although the transmission of incorrect data will not cause problems at the CAN network
level, it can severely disturb the application. A transmit mailbox can be only modified by
software while it is in empty state, refer to Figure 483: Transmit mailbox states.
The filter values can be modified either deactivating the associated filter banks or by setting
the FINIT bit. Moreover, the modification of the filter configuration (scale, mode and FIFO
assignment) in CAN_FMxR, CAN_FSxR and CAN_FFAR registers can only be done when
the filter initialization mode is set (FINIT=1) in the CAN_FMR register.
42.9.2 CAN control and status registers
Refer to Section 1.1 for a list of abbreviations used in register descriptions.
CAN master control register (CAN_MCR)
Address offset: 0x00
Reset value: 0x0001 0002
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DBF
rw
1514131211109876543210
RESET Res. Res. Res. Res. Res. Res. Res. TTCM ABOM AWUM NART RFLM TXFP SLEEP INRQ
rs rw rw rw rw rw rw rw rw
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