ST STM32L4x6 User Manual

Reset and clock control (RCC) RM0351
248/1693 DocID024597 Rev 3
6.4.30 Control/status register (RCC_CSR)
Address: 0x94
Reset value: 0x0C00 0600, reset by system Reset, except reset flags by power Reset only.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWR
RSTF
WWDG
RSTF
IWWG
RSTF
SFT
RSTF
BOR
RSTF
PIN
RSTF
OB L
RSTF
FW
RSTF
RMVF Res. Res. Res. Res. Res. Res. Res.
r r rrrr r rrw
1514131211109 8 765432 1 0
Res. Res. Res. Res. MSISRANGE[3:0] Res. Res. Res. Res. Res. Res.
LSI
RDY
LSION
rw rw rw rw r rw
Bit 31 LPWRRSTF: Low-power reset flag
Set by hardware when a reset occurs due to illegal Stop, Standby or Shutdown mode entry.
Cleared by writing to the RMVF bit.
0: No illegal mode reset occurred
1: Illegal mode reset occurred
Bit 30 WWDGRSTF: Window watchdog reset flag
Set by hardware when a window watchdog reset occurs.
Cleared by writing to the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Bit 29 IWDGRSTF: Independent window watchdog reset flag
Set by hardware when an independent watchdog reset domain occurs.
Cleared by writing to the RMVF bit.
0: No independent watchdog reset occurred
1: Independent watchdog reset occurred
Bit 28 SFTRSTF: Software reset flag
Set by hardware when a software reset occurs.
Cleared by writing to the RMVF bit.
0: No software reset occurred
1: Software reset occurred
Bit 27 BORRSTF: BOR flag
Set by hardware when a BOR occurs.
Cleared by writing to the RMVF bit.
0: No BOR occurred
1: BOR occurred
Bit 26 PINRSTF: Pin reset flag
Set by hardware when a reset from the NRST pin occurs.
Cleared by writing to the RMVF bit.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred

ST STM32L4x6 Specifications

General

Brand	ST
Model	STM32L4x6
Category	Microcontrollers
Language	English