Embedded Flash memory (FLASH) RM0351
78/1693 DocID024597 Rev 3
3 Embedded Flash memory (FLASH)
3.1 Introduction
The Flash memory interface manages CPU AHB ICode and DCode accesses to the Flash
memory. It implements the erase and program Flash memory operations and the read and
write protection mechanisms.
The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines.
3.2 FLASH main features
• Up to 1 MByte of Flash memory with dual bank architecture supporting read-while-write
capability (RWW)
• Memory organization: 2 banks (Bank 1 and Bank 2)
– Main memory: 512 KBytes per bank
– Information block: 32 KBytes per bank
• 72-bit wide data read (64 bits plus 8 ECC bits)
• 72-bit wide data write (64 bits plus 8 ECC bits)
• Page erase (2 KBytes), Bank erase and Mass erase (both banks)
Flash memory interface features:
• Flash memory read operations
• Flash memory program/erase operations
• Read protection activated by option (RDP)
• 4 Write protection areas (2 per bank) selected by option (WRP)
• 2 Proprietary code read protection areas (1 per bank) selected by option (PCROP)
• Prefetch on ICODE
• Instruction Cache: 32 cache lines of 4 x 64 bits on ICode (1 KB RAM)
• Data Cache: 8 cache lines of 4 x 64 bits on DCode (256B RAM)
• Error Code Correction (ECC): 8 bits for 64-bit double-word
• Option byte loader
• Low-power mode
3.3 FLASH functional description
3.3.1 Flash memory organization
The Flash memory is organized as 72-bit wide memory cells (64 bits plus 8 ECC bits) that
can be used for storing both code and data constants.
To Next Page
Loading...
Need help?
General
