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RM0351 Power control (PWR)
178
I/O states in Low-power sleep mode
In Low-power sleep mode, all I/O pins keep the same state as in Run mode.
Entering the Low-power sleep mode
The Low-power sleep mode is entered from low-power run mode according Section :
Entering low power mode, when the SLEEPDEEP bit in the Cortex
®
-M4 System Control
register is clear.
Refer to Table 23: Low-power sleep for details on how to enter the Low-power sleep mode.
Exiting the Low-power sleep mode
The low-power Sleep mode is exit according Section : Exiting low power mode. When
exiting the Low-power sleep mode by issuing an interrupt or an event, the MCU is in Low-
power run mode.
Refer to Table 23: Low-power sleep for details on how to exit the Low-power sleep mode.
5.3.6 Stop 0 mode
The Stop 0 mode is based on the Cortex
®
-M4 deepsleep mode combined with the
peripheral clock gating. The voltage regulator is configured in main regulator mode. In Stop
0 mode, all clocks in the V
CORE
domain are stopped; the PLL, the MSI, the HSI16 and the
Table 23. Low-power sleep
Low-power sleep-now
mode
Description
Mode entry
Low-power sleep mode is entered from the Low-power run mode.
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex
®
-M4 System Control register.
Low-power sleep mode is entered from the Low-power run mode.
On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
– No interrupt is pending
Refer to the Cortex
®
-M4 System Control register.
Mode exit
If WFI or Return from ISR was used for entry
Interrupt: refer to Table 42: STM32L4x6 vector table
If WFE was used for entry and SEVONPEND = 0:
Wakeup event: refer to Section 12.3.2: Wakeup event management
If WFE was used for entry and SEVONPEND = 1:
Interrupt even when disabled in NVIC: refer to Table 42: STM32L4x6
vector table
Wakeup event: refer to Section 12.3.2: Wakeup event management
After exiting the Low-power sleep mode, the MCU is in Low-power run
mode.
Wakeup latency None