ST STM32L4x6 User Manual

Reset and clock control (RCC) RM0351
188/1693 DocID024597 Rev 3
6.2.4 PLL
The device embeds 3 PLLs: PLL, PLLSAI1, PLLSAI2. Each PLL provides up to three
independent outputs. The internal PLLs can be used to multiply the HSI16, HSE or MSI
output clock frequency. The PLLs input frequency must be between 4 and 16 MHz. The
selected clock source is divided by a programmable factor PLLM from 1 to 8 to provide a
clock frequency in the requested input range. Refer to Figure 12: Clock tree and PLL
configuration register (RCC_PLLCFGR).
The PLLs configuration (selection of the input clock and multiplication factor) must be done
before enabling the PLL. Once the PLL is enabled, these parameters cannot be changed.
To modify the PLL configuration, proceed as follows:
1. Disable the PLL by setting PLLON to 0 in Clock control register (RCC_CR).
2. Wait until PLLRDY is cleared. The PLL is now fully stopped.
3. Change the desired parameter.
4. Enable the PLL again by setting PLLON to 1.
5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, PLLREN in PLL
configuration register (RCC_PLLCFGR).
An interrupt can be generated when the PLL is ready, if enabled in the Clock interrupt
enable register (RCC_CIER).
The same procedure is applied for changing the configuration of the PLLSAI1 or PLLSAI2:
1. Disable the PLLSAI1/PLLSAI2 by setting PLLSAI1ON/PLLSAI2ON to 0 in Clock control
register (RCC_CR).
2. Wait until PLLSAI1RDY/PLLSAI2RDY is cleared. The PLLSAI1/PLLSAI2 is now fully
stopped.
3. Change the desired parameter.
4. Enable the PLLSAI1/PLLSAI2 again by setting PLLSAI1ON/PLLSAI2ON to 1.
5. Enable the desired PLL outputs by configuring PLLSAI1PEN/PLLSAI2PEN,
PLLSAI1QEN/PLLSAI2QEN, PLLSAI1REN/PLLSAI2REN in PLLSAI1 configuration
register (RCC_PLLSAI1CFGR) and PLLSAI2 configuration register
(RCC_PLLSAI2CFGR).
The PLL output frequency must not exceed 80 MHz.
The enable bit of each PLL output clock (PLLPEN, PLLQEN, PLLREN, PLLSAI1PEN,
PLLSAI1QEN, PLLSAI1REN, PLLSAI2PEN and PLLSAI2REN) can be modified at any time
without stopping the corresponding PLL. PLLREN cannot be cleared if PLLCLK is used as
system clock.
6.2.5 LSE clock
The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the
advantage of providing a low-power but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in Backup domain control
register (RCC_BDCR). The crystal oscillator driving strength can be changed at runtime
using the LSEDRV[1:0] bits in the Backup domain control register (RCC_BDCR) to obtain
the best compromise between robustness and short start-up time on one side and low-
power-consumption on the other side. The LSE drive can be decreased to the lower drive

ST STM32L4x6 Specifications

General

Brand	ST
Model	STM32L4x6
Category	Microcontrollers
Language	English