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DocID024597 Rev 3 999/1693

RM0351 General-purpose timers (TIM15/16/17)

1009

28.6.9 TIM16&TIM17 prescaler (TIMx_PSC)

Address offset: 0x28

Reset value: 0x0000

28.6.10 TIM16&TIM17 auto-reload register (TIMx_ARR)

Address offset: 0x2C

Reset value: 0xFFFF

Bit 31 UIFCPY: UIF Copy

This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in

TIMx_CR1 is reset, bit 31 is reserved and read as 0.

Bits 30:16 Reserved, must be kept at reset value.

Bits 15:0 CNT[15:0]: Counter value

1514131211109876543210

PSC[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency (CK_CNT) is equal to f

CK_PSC

/ (PSC[15:0] + 1).

PSC contains the value to be loaded in the active prescaler register at each update event

(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger

controller when configured in “reset mode”).

1514131211109876543210

ARR[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 ARR[15:0]: Prescaler value

ARR is the value to be loaded in the actual auto-reload register.

Refer to the Section 28.4.1: Time-base unit on page 934 for more details about ARR update

and behavior.

The counter is blocked while the auto-reload value is null.

ST STM32L4x6 User Manual

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