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Reset and clock control (RCC) RM0351

180/1693 DocID024597 Rev 3

Figure 11. Simplified diagram of the reset circuit

Software reset

The SYSRESETREQ bit in Cortex

-M4 Application Interrupt and Reset Control Register

must be set to force a software reset on the device (refer to the STM32F3xx/F4xx/L4xx

Cortex

-M4 programming manual (PM0214)).

Low-power mode security reset

To prevent that critical applications mistakenly enter a low-power mode, two low-power

mode security resets are available. If enabled in option bytes, the resets are generated in

the following conditions:

1. Entering Standby mode: this type of reset is enabled by resetting nRST_STDBY bit in

User option Bytes. In this case, whenever a Standby mode entry sequence is

successfully executed, the device is reset instead of entering Standby mode.

2. Entering Stop mode: this type of reset is enabled by resetting nRST_STOP bit in User

option bytes. In this case, whenever a Stop mode entry sequence is successfully

executed, the device is reset instead of entering Stop mode.

3. Entering Shutdown mode: this type of reset is enabled by resetting nRST_SHDW bit in

User option bytes. In this case, whenever a Shutdown mode entry sequence is

successfully executed, the device is reset instead of entering Shutdown mode.

For further information on the User Option Bytes, refer to Section 3.4.1: Option bytes

description.

Option byte loader reset

The option byte loader reset is generated when the OBL_LAUNCH bit (bit 27) is set in the

FLASH_CR register. This bit is used to launch the option byte loading by software.

6.1.3 Backup domain reset

The backup domain has two specific resets.

A backup domain reset is generated when one of the following events occurs:

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