SD/SDIO/MMC card host interface (SDMMC) RM0351
1398/1693 DocID024597 Rev 3
Figure 471. Control unit
The control unit is illustrated in Figure 471. It consists of a power management subunit and
a clock management subunit.
The power management subunit disables the card bus output signals during the power-off
and power-up phases.
The clock management subunit generates and controls the SDMMC_CK signal. The
SDMMC_CK output can use either the clock divide or the clock bypass mode. The clock
output is inactive:
• after reset
• during the power-off or power-up phases
• if the power saving mode is enabled and the card bus is in the Idle state (eight clock
periods after both the command and data path subunits enter the Idle phase)
The clock management subunit controls SDMMC_CK dephasing. When not in bypass mode
the SDMMC command and data output are generated on the SDMMCCLK falling edge
succeeding the rising edge of SDMMC_CK. (SDMMC_CK rising edge occurs on
SDMMCCLK rising edge) when SDMMC_CLKCR[13] bit is reset (NEGEDGE = 0). When
SDMMC_CLKCR[13] bit is set (NEGEDGE = 1) SDMMC command and data changed on
the SDMMC_CK falling edge.
When SDMMC_CLKCR[10] is set (BYPASS = 1), SDMMC_CK rising edge occurs on
SDMMCCLK rising edge. The data and the command change on SDMMCCLK falling edge
whatever NEGEDGE value.
The data and command responses are latched using SDMMC_CK rising edge.
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