ST STM32L4x6 User Manual

DocID024597 Rev 3 81/1693
RM0351 Embedded Flash memory (FLASH)
120
3.3.2 Error code correction (ECC)
Data in Flash memory are 72-bits words: 8 bits are added per double word (64 bits). The
ECC mechanism supports:
• One error detection and correction
• Two errors detection
When one error is detected and corrected, the flag ECCC (ECC correction) is set in Flash
ECC register (FLASH_ECCR). If ECCCIE is set, an interrupt is generated.
When two errors are detected, a flag ECCD (ECC detection) is set in FLASH_ECCR
register. In this case, a NMI is generated.
When an ECC error is detected, the address of the failing double word and its associated
bank are saved in ADDR_ECC[20:0] and BK_ECC in the FLASH_ECCR register.
ADDR_ECC[2:0] are always cleared.
Table 7. Flash module - 256 KB dual bank organization
(1)
Flash area Flash memory addresses
Size
(bytes)
Name
Main memory
Bank 1
0x0800 0000 - 0x0800 07FF 2 K Page 0
0x0800 0800 - 0x0800 0FFF 2 K Page 1
0x0800 1000 - 0x0800 17FF 2 K Page 2
0x0800 1800 - 0x0800 1FFF 2 K Page 3
-
-
-
-
-
-
-
-
-
-
-
-
0x0801 F800 - 0x0801 FFFF 2 K Page 63
Bank 2
0x0802 0000 - 0x0802 07FF 2 K Page 256
0x0802 0800 - 0x0802 0FFF 2 K Page 257
0x0802 1000 - 0x0802 17FF 2 K Page 258
0x0802 1800 - 0x0802 1FFF 2 K Page 259
-
-
-
-
-
-
-
-
-
-
-
-
0x0803 F800 - 0x0803 FFFF 2 K Page 319
Information block
Bank 1 0x1FFF 0000 - 0x1FFF 6FFF 28 K
System memory
Bank 2 0x1FFF 8000 - 0x1FFF EFFF 28 K
Bank 1 0x1FFF 7000 - 0x1FFF 73FF 1 K OTP area
Bank 1 0x1FFF 7800 - 0x1FFF 780F 16
Option bytes
Bank 2 0x1FFF F800 - 0x1FFF F80F 16
1. For 256 KB devices, option DUALBANK=1

ST STM32L4x6 Specifications

General

Brand	ST
Model	STM32L4x6
Category	Microcontrollers
Language	English