ST STM32L4x6

DocID024597 Rev 3 1129/1693
RM0351 Inter-integrated circuit (I2C) interface
1177
Figure 365. Master clock generation
Caution: In order to be I
2
C or SMBus compliant, the master clock must respect the timings given
below:
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6&/+
6&/+
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Table 179. I
2
C-SMBUS specification clock timings
Symbol Parameter
Standard-
mode (Sm)
Fast-mode
(Fm)
Fast-mode
Plus (Fm+)
SMBUS
Unit
Min Max Min Max Min Max Min Max
f
SCL
SCL clock frequency
100 400 1000 100 kHz
t
HD:STA
Hold time (repeated) START
condition
4.0 - 0.6 0.26 - 4.0 - µs
t
SU:STA
Set-up time for a repeated
START condition
4.7 - 0.6 0.26 - 4.7 - µs
t
SU:STO
Set-up time for STOP condition
4.0 - 0.6 0.26 - 4.0 - µs