Embedded Flash memory (FLASH) RM0351
84/1693 DocID024597 Rev 3
Figure 3. Sequential 16 bits instructions execution
When the code is not sequential (branch), the instruction may not be present in the currently
used instruction line or in the prefetched instruction line. In this case (miss), the penalty in
terms of number of cycles is at least equal to the number of wait states.
069
:,7+28735()(7&+
#
)
:$,7
'
(
#
)
'
(
#
'
(
)
#
'
(
)
#
'
(
)
:$,7
'
(
)
#
)
'
#
)
#
5HDGLQV *LYHVLQV
LQV
IHWFK
LQV
IHWFK
LQV
IHWFK
LQV
IHWFK
5HDGLQV *LYHVLQV
LQV
IHWFK
LQV
IHWFK
LQV
IHWFK
LQV
IHWFK
:,7+35()(7&+
#
)
:$,7
'
(
#
)
'
(
#
'
(
)
#
'
(
)
#
'
(
)
'
(
)
)
'
#
)
#
5HDGLQV *LYHVLQV
LQV
IHWFK
LQV
IHWFK
LQV
IHWFK
LQV
IHWFK
*LYHVLQV
LQV
IHWFK
LQV
IHWFK
LQV
IHWFK
LQV
IHWFK
#
5HDGLQV 5HDGLQV
#DGGUHVVUHTXHVWHG
))HWFKVWDJH
''HFRGHVWDJH
(([HFXWHVWDJH
'
(
)
#
&RUWH[0SLSHOLQH
$+%SURWRFRO
To Next Page
Loading...
Need help?
General
