To Next Page

To Previous Page

DocID024597 Rev 3 711/1693

RM0351 Random number generator (RNG)

714

In parallel, the analog seed and the dedicated RNG_CLK clock are monitored. Status bits (in

the RNG_SR register) indicate when an abnormal sequence occurs on the seed or when

the frequency of the RNG_CLK clock is too low. An interrupt can be generated when an

error is detected.

24.3.1 Operation

To run the RNG, follow the steps below:

1. Enable the interrupt if needed (to do so, set the IE bit in the RNG_CR register). An

interrupt is generated when a random number is ready or when an error occurs.

2. Enable the random number generation by setting the RNGEN bit in the RNG_CR

3. At each interrupt, check that no error occurred (the SEIS and CEIS bits should be ‘0’ in

the RNG_SR register) and that a random number is ready (the DRDY bit is ‘1’ in the

RNG_SR register). The contents of the RNG_DR register can then be read.

As required by the FIPS PUB (Federal Information Processing Standard Publication) 140-2,

the first random number generated after setting the RNGEN bit should not be used, but

saved for comparison with the next generated random number. Each subsequent generated

random number has to be compared with the previously generated number. The test fails if

any two compared numbers are equal (continuous random number generator test).

24.3.2 Error management

If the CEIS bit is read as ‘1’ (clock error)

In the case of a clock, the RNG is no more able to generate random numbers because the

RNG_CLK clock is not correct. Check that the clock controller is correctly configured to

provide the RNG clock and clear the CEIS bit. The RNG can work when the CECS bit is ‘0’.

The clock error has no impact on the previously generated random numbers, and the

RNG_DR register contents can be used.

If the SEIS bit is read as ‘1’ (seed error)

In the case of a seed error, the generation of random numbers is interrupted for as long as

the SECS bit is ‘1’. If a number is available in the RNG_DR register, it must not be used

because it may not have enough entropy.

What you should do is clear the SEIS bit, then clear and set the RNGEN bit to reinitialize

and restart the RNG.

ST STM32L4x6 User Manual

Questions and Answers: