Advanced-control timers (TIM1/TIM8) RM0351
850/1693 DocID024597 Rev 3
26.4.29 TIM8 option register 3 (TIM8_OR3)
Address offset: 0x64
Reset value: 0x0000 0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 7654 3 2 1 0
Res. Res. Res. Res.
BK2C
MP2P
BK2C
MP1P
BK2IN
P
BK2DFB
K3E
Res. Res. Res. Res. Res.
BK2CMP
2E
BK2CM
P1E
BK2INE
rw rw rw rw rw rw rw
Bits 31:12 Reserved, must be kept at reset value
Bit 11 BK2CMP2P: BRK2 COMP2 input polarity
This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP2
polarity bit.
0: COMP2 input is active low
1: COMP2 input is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
bits in TIMx_BDTR register).
Bit 10 BK2CMP1P: BRK2 COMP1 input polarity
This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP2
polarity bit.
0: COMP1 input is active low
1: COMP1 input is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
bits in TIMx_BDTR register).
Bit 9 BK2INP: BRK2 BKIN2 input polarity
This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together
with the BKP2 polarity bit.
0: BKIN2 input is active low
1: BKIN2 input is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
bits in TIMx_BDTR register).
Bit 8 BK2DFBK3E: BRK2 DFSDM_BREAK[3] enable
This bit enables the DFSDM_BREAK[3] for the timer’s BRK2 input. DFSDM_BREAK[3] output
is ‘ORed’ with the other BRK2 sources.
0: DFSDM_BREAK[3] input disabled
1: DFSDM_BREAK[3] input enabled
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
bits in TIMx_BDTR register).
Bits 7:3 Reserved, must be kept at reset value
Bit 2 BK2CMP2E: BRK2 COMP2 enable
This bit enables the COMP2 for the timer’s BRK2 input. COMP2 output is ‘ORed’ with the
other BRK2 sources.
0: COMP2 input disabled
1: COMP2 input enabled
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
bits in TIMx_BDTR register).
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