DocID024597 Rev 3 745/1693
RM0351 Advanced encryption standard hardware accelerator (AES)
751
25.14.10 AES initialization vector register 1 (AES_IVR1) (IVR[63:32])
Address offset: 0x24
Reset value: 0x0000 0000
Bits 31:0 IVR0[31:0]: initialization vector register (LSB IVR[31:0])
This register must be written before the EN bit in the AES_CR register is set:
The register value has no meaning if:
– The ECB mode (electronic codebook) is selected.
– The CTR or CBC mode is selected in addition with the key derivation.
In CTR mode (counter mode), this register contains the 32-bit counter value.
Reading this register while AES is enabled will return the value 0x00000000.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVR1[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVR1[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 IVR1[31:0]: Initialization vector register (IVR[63:32])
This register must be written before the EN bit in the AES_CR register is set:
The register value has no meaning if:
– The ECB mode (electronic codebook) is selected.
– The CTR or CBC mode is selected in addition with the key derivation or key derivation + decryption
mode.
In CTR mode (counter mode), this register contains the nonce value.
Reading this register while AES is enabled will return the value 0x00000000.
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