DocID024597 Rev 3 845/1693
RM0351 Advanced-control timers (TIM1/TIM8)
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26.4.25 TIM1/TIM8 capture/compare register 6 (TIMx_CCR6)
Address offset: 0x5C
Reset value: 0x0000
26.4.26 TIM1 option register 2 (TIM1_OR2)
Address offset: 0x60
Reset value: 0x0000 0001
1514131211109876543210
CCR6[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 15:0 CCR6[15:0]: Capture/Compare 6 value
CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit
OC6PE). Else the preload value is copied in the active capture/compare 6 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC6 output.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ETR
SEL
[2]
rw
1514131211109876543210
ETRSEL[1:0] Res. Res.
BK
CMP2P
BK
CMP1P
BKINP
BKDFB
K0E
Res. Res. Res. Res. Res.
BK
CMP2E
BK
CMP1E
BKINE
rw rw rw rw rw rw rw rw rw
Bits 31:17 Reserved, must be kept at reset value
Bits 16:14 ETRSEL[2:0]: ETR source selection
This bit selects the ETR input source.
000: ETR legacy mode
001: COMP1 output connected to ETR input
010: COMP2 output connected to ETR input
Other codes reserved
Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK
bits in TIMx_BDTR register).
Bits 13:12 Reserved, must be kept at reset value
Bit 11 BKCMP2P: BRK COMP2 input polarity
This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP
polarity bit.
0: COMP2 input is active high
1: COMP2 input is active low
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK
bits in TIMx_BDTR register).
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