ST STM32L4x6 User Manual

Reset and clock control (RCC) RM0351
224/1693 DocID024597 Rev 3
6.4.16 AHB1 peripheral clock enable register (RCC_AHB1ENR)
Address offset: 0x48
Reset value: 0x0000 0100
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
Bit 14 USART1RST: USART1 reset
Set and cleared by software.
0: No effect
1: Reset USART1
Bit 13 TIM8RST: TIM8 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM8 timer
Bit 12 SPI1RST: SPI1 reset
Set and cleared by software.
0: No effect
1: Reset SPI1
Bit 11 TIM1RST: TIM1 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM1 timer
Bit 10 SDMMC1RST: SDMMC reset
Set and cleared by software.
0: No effect
1: Reset SDMMC
Bits 9:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGRST: SYSCFG + COMP + VREFBUF reset
0: No effect
1: Reset SYSCFG + COMP + VREFBUF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
TSC
EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. CRCEN Res. Res. Res.
FLASH
EN
Res. Res. Res. Res. Res. Res.
DMA2
EN
DMA1
EN
rw rw rw rw

ST STM32L4x6 Specifications

General

Brand	ST
Model	STM32L4x6
Category	Microcontrollers
Language	English