Flexible static memory controller (FSMC) RM0351
356/1693 DocID024597 Rev 3
3-2 MTYP As needed, exclude 0x2 (NOR Flash memory)
1 MUXE 0x0
0 MBKEN 0x1
Table 57. FMC_BTRx bit fields
Bit number Bit name Value to set
31:30 Reserved 0x0
29-28 ACCMOD Don’t care
27-24 DATLAT Don’t care
23-20 CLKDIV Don’t care
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the second access phase (DATAST+1 HCLK cycles for
write accesses, DATAST HCLK cycles for read accesses).
7-4 ADDHLD Don’t care
3-0 ADDSET
Duration of the first access phase (ADDSET HCLK cycles).
Minimum value for ADDSET is 0.
Table 56. FMC_BCRx bit fields (continued)
Bit number Bit name Value to set
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