ST STM32L4x6

System and memory overview RM0351
62/1693 DocID024597 Rev 3
2 System and memory overview
2.1 System architecture
The main system consists of 32-bit multilayer AHB bus matrix that interconnects:
• Five masters:
–Cortex
®
-M4 with FPU core I-bus
–Cortex
®
-M4 with FPU core D-bus
–Cortex
®
-M4 with FPU core S-bus
–DMA1
–DMA2
• Seven slaves:
– Internal Flash memory on the ICode bus
– Internal Flash memory on DCode bus
– Internal SRAM1 (96 KB)
– Internal SRAM2 (32 KB)
– AHB1 peripherals including AHB to APB bridges and APB peripherals (connected
to APB1 and APB2)
– AHB2 peripherals
– The external memory controllers (FMC and QUADSPI).
The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously. This
architecture is shown in Figure 1: