ST STM32L4x6 User Manual

DocID024597 Rev 3 163/1693
RM0351 Power control (PWR)
178
5.4.3 Power control register 3 (PWR_CR3)
Address offset: 0x08
Reset value: 0x0000 8000. This register is not reset when exiting Standby modes and with
the PWRRST bit in the RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
Bit 4 PVME1: Peripheral voltage monitoring 1 enable: V
DDUSB
vs. 1.2V
0: PVM1 (V
DDUSB
monitoring vs. 1.2V threshold) disable.
1: PVM1 (
V
DDUSB
monitoring vs. 1.2V threshold) enable.
Bits 3:1 PLS[2:0]: Power voltage detector level selection.
These bits select the voltage threshold detected by the power voltage detector:
000: V
PVD0
around 2.0 V
001: V
PVD1
around 2.2 V
010: V
PVD2
around 2.4 V
011: V
PVD3
around 2.5 V
100: V
PVD4
around 2.6 V
101: V
PVD5
around 2.8 V
110: V
PVD6
around 2.9 V
111: External input analog voltage PVD_IN (compared internally to VREFINT)
Note: These bits are write-protected when the bit PVDL (PVD Lock) is set in the
SYSCFG_CBR register.
These bits are reset only by a system reset.
Bit 0 PVDE: Power voltage detector enable
0: Power voltage detector disable.
1: Power voltage detector enable.
Note: This bit is write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR
register.
This bit is reset only by a system reset.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
EIWUL Res. Res. Res. Res. APC Res. RRS Res. Res. Res. EWUP5 EWUP4 EWUP3 EWUP2 EWUP1
rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 EIWUL: Enable internal wakeup line
0: Internal wakeup line disable.
1: Internal wakeup line enable.
Bits 14:11 Reserved, must be kept at reset value.

ST STM32L4x6 Specifications

General

Brand	ST
Model	STM32L4x6
Category	Microcontrollers
Language	English